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Computers, IEEE Transactions on

Issue 7 • Date Jul 1990

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Displaying Results 1 - 15 of 15
  • Notes on shuffle/exchange type permutation sets

    Publication Year: 1990 , Page(s): 962 - 965
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    Properties of some shuffle/exchange type permutation sets are studied from operational points of view. The permutation sets studied are Ω, Ω-1, Ψ, L, and U; Ω and Ω-1 are, respectively, the omega and inverse omega permutation sets, Ω≡(Ω∩Ω-1); and L and U are, respectively, the admissible lower and upper triangular permutation sets. Several intuitive operations are introduced. Based on these operations, important known results relating to these sets are readdressed. The recursive nature of the sets is also discussed View full abstract»

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  • Markovian queueing network models for performance analysis of a single-bus multiprocessor system

    Publication Year: 1990 , Page(s): 975 - 980
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    An exact solution for the performance analysis of a typical single-bus multiprocessor system is presented. The multiprocessor system is modeled by a Markovian queueing network. An r-stage hypoexponential distribution or an r-stage hyperexponential distribution is used to represent the nonexponential service times. Consequently, the equilibrium probabilities of two-dimensional Markov chains are expressed by simple recurrence relations. Processing efficiency is used as the primary measure of performance. To investigate the effects of different service time distributions on system performance, comparative results are obtained for a large set of input parameters. The numerical results illustrate that processing efficiency attains its maximum value for a constant (deterministic) service time; if service time of common memory is hypoexponentially distributed, then approximating the service time by an exponential distribution produces less than 6% error on the system performance View full abstract»

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  • Dynamic processor self-scheduling for general parallel nested loops

    Publication Year: 1990 , Page(s): 919 - 929
    Cited by:  Papers (34)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    A processor self-scheduling scheme is proposed for general parallel nested loops in multiprocessor systems. In this scheme, programs are instrumented to allow processors to schedule loop iterations among themselves dynamically at run time without involving the operating system. The scheme has two levels. At the low level, it uses simple fetch-and-op operations to take advantage of the regular structure in the innermost parallel loop nests; at the high level, the irregular structure of the outer loops (parallel or serial) and the IF-THEN-ELSE constructs are handled by using dynamic parallel linked lists. The larger granularity or the processes at the high level easily justifies the added overhead incurred from maintaining such dynamic data structures. The use of guided self-scheduling (GSS) and shortest-delay self-scheduling (SDSS) in this scheme is analyzed View full abstract»

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  • Performance analysis of a message-oriented knowledge-base

    Publication Year: 1990 , Page(s): 951 - 957
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (668 KB)  

    A message-driven model for function-free Horn logic is presented, where the knowledge base is represented as a network of logical processing elements communicating with one another exclusively through messages. The lack of centralized control and centralized memory makes this model suitable for implementation on highly parallel asynchronous computer architecture. The performance of this message-driven system is analyzed and compared to that of a sequential resolution scheme using backtracking. Closed-form expressions for both approaches are derived View full abstract»

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  • Minimal order loop-free routing strategy

    Publication Year: 1990 , Page(s): 870 - 881
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (816 KB)  

    A multiorder routing strategy is developed which is loop-free even in the presence of link/node failures. Unlike most conventional methods in which the same routing strategy is applied indiscriminately to all nodes in the network, nodes under this proposal may adopt different routing strategies according to the network structure. Formulas are developed to determine the minimal order of routing strategy for each node to eliminate looping completely. A systematic procedure for striking a compromise between the operational overhead and network adaptability is proposed. Several illustrative examples are presented View full abstract»

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  • Analysis of checksums, extended-precision checksums, and cyclic redundancy checks

    Publication Year: 1990 , Page(s): 969 - 975
    Cited by:  Papers (15)  |  Patents (38)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (668 KB)  

    The effectiveness of extended-precision checksums is thoroughly analyzed. It is demonstrated that the extended-precision checksums most effectively exploit natural redundancy occurring in program codes. Honeywell checksums and cyclic redundancy checks are compared to extended-precision checksums. Two's complement, unsigned, and one's complement arithmetic checksums are treated in a unified manner. Results are also extended to any general radix-p arithmetic checksum. Asymptotic and closed-form formulas of aliasing probabilities for the various error models are derived View full abstract»

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  • Performance analysis of real-time software supporting fault-tolerant operation

    Publication Year: 1990 , Page(s): 906 - 918
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1152 KB)  

    Analyzing the performance of real-time control systems featuring mechanisms for online recovery from software faults is discussed. The application is assumed to consist of a number of interacting cyclic processes. The underlying hardware is assumed to be a multiprocessor, possibly with a separate control processor. The software structure is assumed to use design diversity along with forward and/or backward recovery. A detailed but efficiently solvable model for predicting various performance and reliability characteristics is developed. One of the key ideas used in modeling is hierarchical decomposition, which enables computation of level-oriented performance parameters in an efficient manner. The model is general, and adaptable for a number of useful special cases View full abstract»

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  • Clock skew optimization

    Publication Year: 1990 , Page(s): 945 - 951
    Cited by:  Papers (213)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS View full abstract»

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  • An efficient channel routing algorithm to yield an optimal solution

    Publication Year: 1990 , Page(s): 957 - 962
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    An algorithm known as optimal channel routing (OCR) is proposed which finds an optimal solution for the channel routing problem in VLSI design. The algorithm is an A* algorithm with good heuristics and dominance rules for terminating unnecessary nodes in the searching tree. Experimental results, agreeing with theoretical analysis, show that it behaves quite well in average cases. An optimal solution is obtained for the Deutsch difficult case in 5.5-min-CPU time after the algorithm is implemented in Pascal and run on a VAX 11/750 computer View full abstract»

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  • On job assignment for a parallel system of processor sharing queues

    Publication Year: 1990 , Page(s): 858 - 869
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (975 KB)  

    Two of the optimality criteria most commonly considered to compare job assignment policies, namely, the stochastic order and the average total completion time criterion, are discussed. It is shown that the latter, while being weaker than the former, still provides a useful criterion when policies are to be evaluated in terms of average performance measures such as the system average response time. Some of the most relevant results available in the literature on job assignment to parallel first come, first served (FCFS) servers are summarized. The assignment problem is discussed for a parallel system of processor sharing (PS) queues with exponential interarrival times and exponential and identical service requirements. The optimality of the join-the-shortcut-queue (JSQ) assignment policy for this case is proven. Feasible policies for general service time distribution are discussed. An approach allowing a meaningful comparison of servers in the perspective of job assignment is proposed. A comparison of the assignment problem for FCFS and PS parallel systems is presented. View full abstract»

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  • The B-network: a multistage interconnection network with backward links

    Publication Year: 1990 , Page(s): 966 - 969
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    A multistage interconnection network (MIN) for multiprocessor systems is proposed. The proposed MIN, called the B-network, uses backward links to provide backward paths for the requests blocked at switches or memory due to contentions. The gamma network is known to contain a cube network (specifically, the inverse omega network) as a substructure. The B-network is obtained from the gamma network by preserving the cube structure but reversing the direction of all other links. These backward links are used as alternate paths for requests blocked due to path or memory contentions. The B-network can be controlled by the simple destination tag control algorithm; packets navigating through the B-network, using both regular forward links and backward links, can reach their destinations under the destination tag control. The performance of the B-network is analyzed under the uniform traffic model and compared to various networks of interest. It is shown that the B-network surpasses the performance of the gamma network, the crossbar switch, and single-buffered MINs based on (2×2) switches, while having the same hardware complexity as the gamma network View full abstract»

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  • Constructing optimal procedures for testing series systems

    Publication Year: 1990 , Page(s): 943 - 945
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    An efficient algorithm to construct testing procedures for optimally identifying a single defective unit in a series system is presented. A series system such as a local loop of telephone networks is modeled as a sequence of units. The costs incurred by the testing process are general; traveling costs and testing costs are taken into consideration. Although the model assumes that only one defective unit exists in the system, the testing tree still leads to the isolation of a defective unit if two or more exist. This occurs because whenever one proceeds to a subtree, a defective unit corresponding to a vertex within that subtree is certain to exist View full abstract»

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  • (SM)2-II: a large-scale multiprocessor for sparse matrix calculations

    Publication Year: 1990 , Page(s): 889 - 905
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1180 KB)  

    (SM)2-II is a large-scale parallel machine dedicated to scientific computation which includes sparse matrix calculations. In order to connect thousands of microprocessors and utilize a high degree of parallelism, the whole (SM)2-II system is designed based on a simple computational model called the node and connecting-line (NC) model. The concept and the architecture of (SM)2-II are described. The NC-model and a language called node oriented concurrent C (NCC) are derived. The concurrent process controller is briefly introduced. Receiver selectable multicast (RSM) is proposed, and the structure which allows connection of a large number of processing units is described. The performance of the RSM is analyzed. Some connection structures for clusters are evaluated. An operational prototype is introduced View full abstract»

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  • The jitter model for metastability and its application to redundant synchronizers

    Publication Year: 1990 , Page(s): 930 - 942
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    A synchronizer timing model, called the jitter model, which has general application to metastable reliability analysis, is proposed and analyzed. The jitter model is applied to show that redundancy cannot improve the metastable reliability of synchronizers, contradicting previous work by A. El-Amawy (see ibid., vol.38, no.5, p.750-3 (1989)). The jitter model extends previous synchronizer input timing models by incorporating the effects of circuit noise. The circuit noise translates into jitter or random time displacement of a previously proposed deterministic aperture mode. The jitter model is supported by simulation, circuit analysis, and experimental work. The results of a SPICE simulation of a CMOS D-type flip-flop are presented. An experimental bistable device is constructed to examine the behavior of synchronizers with noise. Statistical results obtained from the experimental bistable device support the jitter model for metastability. The sensitivity of metastable reliability of redundant synchronizers to modeling assumptions is highlighted View full abstract»

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  • An efficient deadlock avoidance technique

    Publication Year: 1990 , Page(s): 882 - 888
    Cited by:  Papers (11)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    A deadlock avoidance technique, based on a method of representing directed acyclic graphs, is presented. This technique is suitable for systems with single resources of each resource type. The deadlock avoidance problem considered is the problem of changing a directed acyclic graph while keeping it acyclic. The resource allocation algorithm involves three operations on edges corresponding to release of a resource from a process, unsuccessful allocation of a resource to a process, and successful allocation of a resource to a process, where the allocations include a previous detection of cycles. A path matrix representation is used, making it possible to detect cycles efficiently. The low cost of cycle detection can amortize the cost of the other operations and linear (or even constant) amortized time for one operation can be attained in dense systems View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org