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Computer

Issue 6 • June 1990

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Displaying Results 1 - 12 of 12
  • Comments, with reply, on 'Urgency of ethical standards intensifies in computer community' (Standards)

    Publication Year: 1990
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (167 KB)

    The commentator writes in defense of ethical relativism, maintaining that M.C. McFarland (ibid., vol.23, no.3, p.77-81, Mar. 1990) has confused it with ethical nihilism. He argues that ethical relativism is completely consistent with a professional society's formation of ethical standards. McFarland replies that he and the commentator agree on the definition of ethical relativism but differ on its... View full abstract»

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  • Comments, with reply on 'A hierarchical taxonomic system for computer architectures'

    Publication Year: 1990
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (167 KB)

    The commentator observes that the classification used in the above article (ibid., vol.23, no.3, p.64-74, Mar. 1990) is arbitrary and that truly significant properties of computer architectures, like topologies and communication methods, are missing entirely. The author responds that to the extent a taxonomic scheme represents a particular viewpoint, all such schemes have an element of arbitrarine... View full abstract»

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  • A survey of cache coherence schemes for multiprocessors

    Publication Year: 1990, Page(s):12 - 24
    Cited by:  Papers (151)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1016 KB)

    Schemes for cache coherence that exhibit various degrees of hardware complexity, ranging from protocols that maintain coherence in hardware, to software policies that prevent the existence of copies of shared, writable data, are surveyed. Some examples of the use of shared data are examined. These examples help point out a number of performance issues. Hardware protocols are considered. It is seen... View full abstract»

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  • Translation-lookaside buffer consistency

    Publication Year: 1990, Page(s):26 - 36
    Cited by:  Papers (20)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1173 KB)

    Nine solutions to the cache consistency problem for shared-memory multiprocessors with multiple translation-lookaside buffers (TLBs) are described. A TLB's function is defined, and it is shown how TLB inconsistency arises in uniprocessor and multiprocessor architectures. The problem of TLB consistency is solved in a uniprocessor and in multiprocessors with a shared bus, virtual-address caches, and... View full abstract»

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  • Compiler-directed cache management in multiprocessors

    Publication Year: 1990, Page(s):39 - 47
    Cited by:  Papers (29)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1130 KB)

    The necessity of finding alternatives to hardware-based cache coherence strategies for large-scale multiprocessor systems is discussed. Three different software-based strategies sharing the same goals and general approach are presented. They consist of a simple invalidation approach, a fast selective invalidation scheme, and a version control scheme. The strategies are suitable for shared-memory m... View full abstract»

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  • Directory-based cache coherence in large-scale multiprocessors

    Publication Year: 1990, Page(s):49 - 58
    Cited by:  Papers (110)  |  Patents (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1330 KB)

    The usefulness of shared-data caches in large-scale multiprocessors, the relative merits of different coherence schemes, and system-level methods for improving directory efficiency are addressed. The research presented is part of an effort to build a high-performance, large-scale multiprocessor. The various classes of cache directory schemes are described, and a method of measuring cache coherence... View full abstract»

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  • Synchronization algorithms for shared-memory multiprocessors

    Publication Year: 1990, Page(s):60 - 69
    Cited by:  Papers (55)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1022 KB)

    A performance evaluation of the Symmetry multiprocessor system revealed that the synchronization mechanism did not perform well for highly contested locks, like those found in certain parallel applications. Several software synchronization mechanisms were developed and evaluated, using a hardware monitor, on the Symmetry multiprocessor system; the mechanisms were to reduce contention for the lock.... View full abstract»

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  • Scalable shared-memory multiprocessor architectures

    Publication Year: 1990, Page(s):71 - 74
    Cited by:  Papers (16)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (370 KB)

    Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all proc... View full abstract»

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  • Distributed-directory scheme: scalable coherent interface

    Publication Year: 1990, Page(s):74 - 77
    Cited by:  Papers (57)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (450 KB)

    The scalable coherent interface (SCI), a local or extended computer backplane interface being defined by an IEEE standard project (P1596), is discussed. the interconnection is scalable, meaning that up to 64 K processor, memory, or I/O nodes can effectively interface to a shared SCI interconnection. The SCI sharing-list structures are described, and sharing-list addition and removal are examined. ... View full abstract»

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  • Distributed-directory scheme: Stanford distributed-directory protocol

    Publication Year: 1990, Page(s):78 - 80
    Cited by:  Papers (23)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    The Stanford distributed-directory (SDD) cache-coherence protocol, based on a singly linked list of distributed directories, is examined. Sharing-list additions and removals are explained diagramatically. Reads, writes, pending signals, replacement, and synchronization are discussed. Replacing lines linked in a list is done by invalidating the lower part of the list. A doubly linked list may be us... View full abstract»

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  • Multiple-bus shared-memory system: Aquarius project

    Publication Year: 1990, Page(s):80 - 83
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (415 KB)

    A multiple-bus architecture called a multi-multi is presented. The architecture is designed to handle several dimensions with a moderate number of processors per bus. It provides scaling to a large number of processors in a system. A key characteristic of the architecture is the large amount of bandwidth it provides. Each node in the architecture contains a microprocessor, memory, and a cache. The... View full abstract»

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  • Standards-establishing a standard metrics program

    Publication Year: 1990, Page(s):85 - 86
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    Guidelines for establishing a standard metrics program for organizations are presented. Initially, it is suggested that the collection effort be minimal, meaning the data to be processed should already be in the collection phase so that the total metrics effort will not be viewed as a burden; the raw metric data must be such that it can be processed automatically; the initial metrics effort should... View full abstract»

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Aims & Scope

Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed articles written for and by computer researchers and practitioners representing the full spectrum of computing and information technology, from hardware to software and from emerging research to new applications. 

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Editor-in-Chief
Sumi Helal
Lancaster University
sumi.helal@computer.org