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Components and Packaging Technologies, IEEE Transactions on

Issue 2 • Date June 2001

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Displaying Results 1 - 25 of 25
  • A methodology for the design of perforated tiles in raised floor data centers using computational flow analysis

    Page(s): 177 - 183
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB)  

    An important aspect of the design of data centers involves sizing of the perforated floor tiles for return of cold air, the size of the space under the raised floor, and placement of the DP equipment and modular chillers. The flow through individual perforated tiles needs to fulfil the cooling requirements of the computer equipment placed adjacent to them. The novelty of this paper lies in the treatment of the volume under the raised floor as a uniformly pressurized plenum. The accuracy of the Pressurized Plenum model is demonstrated with reference to a computational fluid dynamics (CFD) analysis of the recirculating flow under the raised floor and the limits of its validity are also identified. The simple model of the volume under the raised floor enables use of the technique of flow network modeling (FNM) for the prediction of the distribution of flow rates exiting from the various tiles. An inverse design method is proposed for one-step design of the perforated tiles and flow balancing plates for individual chillers. Subsequent use of the FNM technique enables assessment of the performance of the actual system. Further, required design changes to an existing system can also be evaluated using the FNM analysis in a simple, quick, and accurate manner. The resulting design approach is very simple and efficient, and is well suited for the design of modern data centers. View full abstract»

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  • Editorial

    Page(s): 308
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    Freely Available from IEEE
  • Computational parameter study of chip scale package array cooling

    Page(s): 184 - 190
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    This paper describes the results of a computational investigation into the thermal management of chip scale package arrays. The parameters considered include power dissipation, cooling air inlet velocity, module spacing, and circuit board conductivity. The geometry used throughout the study was an array of five modules placed on board with forced air cooling along the axis of the array both above and below the circuit board. Each module was the same size and dissipated the same amount of power. Free convection was included with gravity aligned normal to the plane of the circuit board. The effects of thermal radiation were neglected and the flow was considered to be laminar. Three dimensional solutions were generated using the commercial computational fluid dynamics code FLOTHERM. Results are presented in the form of thermal resistances for each package in the array. A number of interesting results were found. For the case of low conductivity circuit boards, the resistance for the first package in the array was a function of inlet velocity only. However, this was not the case when power planes were present and energy was conducted more effectively along the board. For low inlet velocities, when there are strong natural convection effects, there was a temperature overshoot where the highest temperature does not occur in the last package of the array. Finally, when the effects of natural convection were small, the thermal resistance was relatively insensitive to the power dissipation View full abstract»

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  • Optimization of plate fin heat sinks using entropy generation minimization

    Page(s): 159 - 165
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB) |  | HTML iconHTML  

    The specification and design of heat sinks for electronic applications is not easily accomplished through the use of conventional thermal analysis tools because “optimized” geometric and boundary conditions are not known a priori. A procedure is presented that allows the simultaneous optimization of heat sink design parameters based on a minimization of the entropy generation associated with heat transfer and fluid friction. All relevant design parameters for plate fin heat sinks, including geometric parameters, heat dissipation, material properties and flow conditions can be simultaneously optimized to characterize a heat sink that minimizes entropy generation and in turn results in a minimum operating temperature. In addition, a novel approach for incorporating forced convection through the specification of a fan curve is integrated into the optimization procedure, providing a link between optimized design parameters and the system operating point. Examples are presented that demonstrate the robust nature of the model for conditions typically found in electronic applications. The model is shown to converge to a unique solution that gives the optimized design conditions for the imposed problem constraints View full abstract»

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  • The effect of power cycling on the reliability of lead-free surface mount assemblies

    Page(s): 241 - 249
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    A power cycling in-test monitoring system has been constructed to test the reliability of eight different lead-free surface mount assemblies. The assemblies included SnAg3.8Cu0.7 and SnAg3.8Cu0.7X solder joints on OSP-Cu (organic solderability preservative on Cu), electroless NiAu, immersion Ag and immersion Sn board metallizations. One Pb containing assembly, Sn62PbAg2 on OSP-Cu board metallization, was included for comparison. The components on the assemblies were 1206 resistors (Sn100 metallization on the end terminals) and 100 lead QFP with gullwing leads (SnPb15 metallization). All assemblies experienced up to 5000 power cycles of ambient to 100°C with a 15 min dwell at each temperature. Solder joint reliability was evaluated by monitoring electrical resistance after each power cycle and examining mechanical strength and microstructure with number of power cycles. The 1206 resistors on four of the assemblies (one of which was the Pb containing assembly) exhibited electrical resistance increases after 4000 power cycles. All resistor samples decreased in strength by more than 70% at 5000 cycles and cracks appeared after 1000 power cycles. All gullwing lead solder joints exhibited good reliability over 5000 power cycles, with no resistance increase and no strength reduction. Small cracks appeared after 3000 power cycles View full abstract»

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  • Thermal characterization of a liquid cooled AlSiC base plate with integral pin fins

    Page(s): 213 - 219
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    In this study, we present the thermal analysis and experimental performance assessment of an aluminum silicon carbide (AlSiC) metal matrix composite (MMC) base plate with integral cooling fins. By attaching a pin-finned base plate to an open-chambered flow-through heat sink, the mechanical interface between the base plate and cooling medium is eliminated. This reduces the overall thermal resistance and improves module reliability as compared with traditional base plate cooling schemes. Computational fluid dynamics and heat transfer techniques were employed to model the thermal and hydrodynamic resistance characteristics through the pin fin structure of a prototype base plate design. A unit-cell approach was employed to avoid the computational expense of modeling the entire pin array. Performance was verified experimentally in a closed loop test facility using water as the cooling fluid. It was found that the unit-cell approach produced good agreement with experimental pressure drop and heat transfer results View full abstract»

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  • Assessment of high-heat-flux thermal management schemes

    Page(s): 122 - 141
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    This paper explores the recent research developments in high-heat-flux thermal management. Cooling schemes such as pool boiling, detachable heat sinks, channel flow boiling, microchannel and mini-channel heat sinks, jet-impingement, and sprays, are discussed and compared relative to heat dissipation potential, reliability, and packaging concerns. It is demonstrated that, while different cooling options can be tailored to the specific needs of individual applications, system considerations always play a paramount role in determining the most suitable cooling scheme. It is also shown that extensive fundamental electronic cooling knowledge has been amassed over the past two decades. Yet there is now a growing need for hardware innovations rather than perturbations to those fundamental studies. An example of these innovations is the cooling of military avionics, where research findings from the electronic cooling literature have made possible the development of a new generation of cooling hardware which promise order of magnitude increases in heat dissipation compared to today's cutting edge avionics cooling schemes View full abstract»

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  • A study of compact thermal model topologies in CFD for a flip chip plastic ball grid array package

    Page(s): 191 - 198
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB) |  | HTML iconHTML  

    A previously validated detailed model of a 119-pin flip-chip plastic ball grid array (FC-PBGA) package was created and validated against experimental data for natural convection and forced convection environments. Next, two compact models mere derived, a two-resistor model (created using the JEDEC-standard based computational approach), and a multiresistor model (created using the DELPHI optimization approach that was boundary condition independent within engineering accuracy). The compact models were placed in natural convection and forced convection (velocities of 1 and 2 m/s) environments with and without a heatsink. Based on the agreement obtained between the detailed model and compact model simulations, the accuracy and validity of the two compact models was assessed. Of the two compact thermal models considered, the Delphi multiresistor model provided the same predictive estimates (within 5%) as simulations involving a detailed thermal model of the package in natural and forced convection environments both with and without attached heatsinks. Some thermal modeling issues were addressed with respect to implementation of compact thermal models with attached heatsinks View full abstract»

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  • On the design parameters of flip-chip PBGA package assembly for optimum solder ball reliability

    Page(s): 300 - 307
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB) |  | HTML iconHTML  

    An experimental investigation of the warpage of a flip-chip plastic ball grid array package assembly is presented and a critical deformation mode is identified. The experimental data, documented while cooling the assembly from the underfill curing temperature to -40°C, clearly reveal the effect of the constraints from the chip and the PCB on the global behavior of the substrate. The constraints produce an inflection point of the substrate at the edge of the chip. An experimentally verified three-dimensional (3-D) nonlinear finite element analysis proceeds to quantify the effect of the substrate behavior on the second-level solder ball strains. An extensive parametric study is conducted to identify the most critical design parameter for optimum solder ball reliability View full abstract»

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  • Modeling of the thermal and hydraulic performance of plate fin, strip fin, and pin fin heat sinks-influence of flow bypass

    Page(s): 142 - 149
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    Tests have been conducted in a wind tunnel with seven types of heat sinks including plate fin, strip fin, and pin fin heat sinks. In the case of strip fin, and pin fin heat sinks, both in-line and staggered arrays have been studied. The pin fin heat sinks had circular and square cross-sections. For each type, tests were run with fin heights (H) of 10, 15, and 20 mm while the heat sink width (B) was kept constant and equal to 52.8 mm. In total, 42 different heat sinks were tested. The width of the wind tunnel duct (CB) was varied in such a way that results were obtained for B/CB=0.84, 0.53, and 0.33. The wind tunnel height (CH) was varied similarly, and data were recorded for H/CH=1, 0.67, and 0.33 while the duct Reynolds number was varied between 2000 through 16500. An empirical bypass correlation has been developed for the different fin designs. The correlation predicts the Nusselt number and the dimensionless pressure drop and takes into account the influence of duct height, duct width, fin height, fin thickness, and fin-to-fin distance. The correlation parameters are individual for each fin design. Further, a physical bypass model for plate fin heat sinks has been developed to describe the bypass effect View full abstract»

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  • Immersion-cooled heat sinks for electronics: insight from high-speed photography

    Page(s): 166 - 176
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    The development of effective heat sinks for the primary heat-dissipating component of a typical portable electronics device is an ongoing challenge. Thermal management using air-cooling is limited by the inherently limited thermal properties of the coolant. Other alternatives, including liquid immersion cooling, phase-change materials, and heat pipes, may merit consideration if the basic mechanisms can be reliably predicted. This study sheds light on the nucleation characteristics of an etched cavity-enhanced surface for use in an immersion-cooled heat sink. The target application is a high-density multichip module with several heat dissipating sources. High-speed photography was used to record parameters such as bubble interactions, bubble size, departure frequency and active site density while varying the cavity spacing and heat flux. The cavities, which have a characteristic dimension of approximately 40 μm, are arranged in a square cluster 12.7 mm on each side. It was determined that the contribution of latent heat as a heat dissipation mechanism is only minor (less than 16%). In addition, it is proposed that the latent heat dissipation percentage may be used as a thermal performance indicator. Interactions between neighboring heat sources were also studied. These interactions decreased the bubble departure frequency and thereby affected the latent heat contribution View full abstract»

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  • Statistics of electric conductance through anisotropically conductive adhesive

    Page(s): 250 - 255
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB) |  | HTML iconHTML  

    We have investigated the electric conductance between two contacts electrically interconnected by an anisotropically conductive adhesive (ACA). It is first demonstrated that as compared with the symmetric equipotential profile of a point contact between two half infinitely large conducting materials, the spatial distribution of the equipotential profile becomes deformed when the contact is close to the edge of the conducting material. The electric potentials of two contacts also redistribute when the two contacts are brought together in nearby vicinity. By simulating the metal fillers spatial distributions in an ACA, we have shown that the spatial uniformity of the electric conduction between two contacts depends on the number of metal particles that interconnect the two contacts. Increasing the number of metal fillers on the contact pad improves the uniformity of the electric conduction. It however also increases the constriction resistances due to fellow particles so that the total conductance does not increase in the additive manner View full abstract»

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  • Interfacial fracture toughness for delamination growth prediction in a novel peripheral array package

    Page(s): 265 - 270
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    The objective of this study is to predict interfacial delamination propagation that may inhibit the performance of a novel surface mountable, high input/output (I/O) electronic package. Incorporation of such predictions in the design phase of the package can lead to judicial selection of materials and geometric parameters such that the interfacial delamination based failures can be avoided. This, in turn, leads to significant cost savings and shorter time-to-market due to the shortening of the prototyping and qualification testing phases. The focus of the present study is the prediction of potential delaminations at the encapsulant-backplate interface in a very small peripheral array (VSPA) package during manufacturing. The delamination growth prediction is based on the comparison of interfacial fracture parameters obtained from the numerical simulations to appropriate critical values determined experimentally using controlled fracture toughness tests. In this paper, the fracture toughness of the encapsulant/backplate interface is characterized using a fracture toughness test that requires simple test specimen, fixture and loading geometries. The critical interfacial fracture toughness and the fracture mode mixity are determined using closed-form and finite element analyses of the test specimen geometries, taking into consideration the effects of thermo-mechanical residual stresses resulting from the test specimen fabrication process. Furthermore, an experimental characterization of the encapsulant material is also conducted in order to assess the effects of its time- and temperature-dependent thermomechanical response on the fracture toughness of the encapsulant-backplate interface View full abstract»

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  • Modeling contact between rigid sphere and elastic layer bonded to rigid substrate

    Page(s): 207 - 212
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB) |  | HTML iconHTML  

    An approximate mechanical model is developed for predicting the radius of contact between a sphere and a layered substrate. The complex solution of Chen and Engel is reduced to the simple root finding procedure for the unknown contact radius. Numerical data from the model of Chen and Engel are obtained for several combinations of layer material. It is shown that with the proper selection of dimensionless parameters the numerical results fall on a single curve that is easily correlated. Radius predictions show good agreement with experimental measurements View full abstract»

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  • High heat flux heat pipe mechanism for cooling of electronics

    Page(s): 220 - 225
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    This paper discusses an advanced heat pipe mechanism that has the potential of achieving heat flux capabilities over 250 W/cm2. The mechanism utilizes thermally driven pulsating two-phase flow to achieve high heat flux capability and heat transfer coefficient. A simplified hydrodynamic model in was developed to guide the proof-of-concept heat pipe design. A more detailed numerical model was also developed and will be solved to predict the heat pipe's thermal performance. Test results of proof-of-concept heat pipes verified the heat flux capability of the advanced mechanism and the accuracy of the simplified model. Pulsating heat pipes are feasible approaches to removing increasing heat dissipation densities in electronic equipment View full abstract»

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  • Design for manufacturability of SISE parallel plate forced convection heat sinks

    Page(s): 150 - 158
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    The study reported herein extends a previously reported “design for manufacturability” methodology, to forced convection cooled rectangular plate heat sinks. Using a well validated analytical model, the thermofluid performance of the side-inlet-side-exit (SISE) heat sink has been characterized, parametric optimization carried out, and the maximum heat transfer capabilities for a range of operating points has been determined. A least-material optimization has been performed to achieve optimal material use. The analysis indicates the least-material design to provide significant mass savings for a moderate penalty in thermal performance. Empirical criteria for manufacturability obtained from several heat sink manufacturers lead to qualitative guidelines View full abstract»

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  • RF electrical measurements of fine pitch BGA packages

    Page(s): 233 - 240
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    A series of fine pitched ball grid arrays (BGAs) were measured on an Network Analyzer using a novel technique to de-embed the package test fixture and provide an accurate representation of the electrical characteristics of the package. The technique consisted of the design and fabrication of a RF circuit board. Duplicates of the board were modified to become a series of calibration fixtures while others, with sample packages attached, were modified to become test fixtures. The packages, attached to circuit boards, were measured to determine their performance at the RF frequencies of most cellular phone applications. Measurements included the return losses looking into several leads of the package that were 50 Ω terminated and insertion losses from one terminated lead to an adjacent one. These measurements can be used for verifying models or for characterizing packages View full abstract»

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  • Numerical modeling of interfacial delamination propagation in a novel peripheral array package

    Page(s): 256 - 264
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    Interfacial delamination, due to the presence of dissimilar material systems, is one of the primary concerns in electronic package designs. The mismatch in the coefficient of thermal expansion between the different layers in the package can generate high interfacial stresses upon heating or cooling of the structure during fabrication, assembly, or in field use. These stresses, if sufficiently large, can compromise the adhesive integrity of the interface. The propagation of the resulting delamination along an interface can degrade or completely destroy the functionality of the system. The focus of this study is to examine the potential for interfacial delamination propagation in current and future versions of a novel peripheral array package. Two-dimensional (2-D) and three-dimensional (3-D) numerical models were constructed of this package with cracks embedded along a critical interface. The energy release rate associated with interfacial fracture was determined by employing the global energy balance and the crack closure technique. The fracture mode mixity was determined using the crack surface displacement method. These critical fracture parameters were compared with experimentally determined interfacial fracture toughness data to determine the possibility of delamination growth. A material parametric study was also completed using the numerical models with pre-existing delaminations to identify material property trends that would lower the potential for failure. Also, the effect of plastic behavior on interfacial crack growth was studied through J-integral calculations View full abstract»

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  • Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies

    Page(s): 285 - 292
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (556 KB) |  | HTML iconHTML  

    The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mechanics with finite element method. Furthermore, an empirical equation for predicting the thermal-fatigue life of flip chip solder joints is proposed View full abstract»

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  • Reliability of soldered joints in CSPs of various designs and mounting conditions

    Page(s): 293 - 299
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    The chip size package (CSP) is being used in various portable electronic products recently. Further evaluation of the reliability of its soldered joints is required all the more now because those soldered joints are invisible. This study focused on the thermal fatigue life of soldered joints in the CSP. CSPs were mounted on printed circuit boards (PCBs) in various configurations and mounting conditions, and underwent thermal cycle testing. Then, the fatigue lives of their soldered joints were compared. As a result, the following two facts became apparent. First, reflowing at a 210°C peak tends to result in failures that may be derived from poor wetting between solder and pad, in cases where the CSP is mounted on a nickel and gold plated pad. And second, the size of the soldered joint has a great influence on its fatigue life. The larger the soldered joints that we made, the longer fatigue life they indicated. A finite element method (FEM) analysis of those mounted structures was also executed. Viscoplastic (creep and plastic) property of solder was evaluated to compute equivalent inelastic strain occurring in the joints. A parameter in the Coffin-Manson equation is obtained from the computed inelastic strain amplitudes and the experimented actual fatigue lives. This result will enable estimation of the fatigue life of soldered joints of the CSP without actual tests View full abstract»

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  • A novel approach to the design of complex heat transfer systems: portable computer design-a case study

    Page(s): 199 - 206
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB) |  | HTML iconHTML  

    The paper describes a novel approach to solving heat transfer problems in geometrically complex systems. In the present approach, instead of simulating the detailed complex geometry, templates of components and devices are assumed rather than working on actual components. By varying the template dimensions a systematic study on the effects of geometrical configurations on cooling airflow and heat transfer is made possible. The application of the approach is illustrated drawing examples from heat transfer analysis of portable computers. The purpose of the study is to develop a methodology whereby the packaging designer is freed from the task of performing detailed numerical analysis. Currently available numerical analysis tools such as computational fluid dynamics (CFD) codes are given a role in an undertaking to create databases from which fast design codes are developed View full abstract»

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  • Photonics challenge to electronic packaging

    Page(s): 309 - 311
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (92 KB) |  | HTML iconHTML  

    Photonics packaging is a challenge to electronic packaging for two important reasons. The first and most obvious is that light must have access to the device. There must be a window, port or optical fiber interface. The other and more serious problem is that most devices require a highly controlled atmosphere. And if having to accommodate both electrons and photons were not enough, innovators have added mechanical motion to optical devices. Micro-opto-electro-mechanical systems (MOEMS) bring photonics, electronics, optics, physics and mechanical engineering together on one semiconductor device. This appears to be the ultimate convergence of technology domains and can also include biology and chemistry View full abstract»

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  • Advanced thermal tester for accurate measurement of internal thermal resistance of high power electronic modules

    Page(s): 226 - 232
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB) |  | HTML iconHTML  

    A thermal tester has been developed for the accurate measurement of the internal thermal resistance of high-power electronic modules. The tester is designed for the simultaneous measurement of 20 electronic modules each dissipating in excess of 200 W. The heat dissipated is transmitted to the ambient by water-cooled cold plates dedicated to each test site. The tester system layout, mounting assembly, hydraulic design, cold-plate spreader design and data acquisition instrumentation are described. Sample measurements and the associated uncertainty are also discussed. The sample results are validated by comparison with thermal modeling View full abstract»

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  • Software-based analysis of radio frequency plasma display panel for efficient design and impedance matching

    Page(s): 279 - 284
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    A full software analysis technique for the radio frequency (RF) plasma display panel (PDP) has been developed. The RF PDP test panel has been analyzed by the segmentation/three-dimensional (3-D) parameter extraction/SPICE simulation scheme, which was originally developed for the analysis of RF complimentary metal oxide semiconductor (CMOS) chips. Our technique is shown to be accurate in predicting the input impedance of the RF port and the calculated input impedance is used to perform impedance matching of the system. The technique is also extendable to a much larger size RF-PDP and has the possibility of being applied to the design and analysis of various interesting RF systems and components View full abstract»

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  • Application of Al/PI composite bumps to COG bonding process

    Page(s): 271 - 278
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    This work demonstrates the probing, testability and applicability of Al/PI (aluminum/polyimide) composite bumps to the chip on-glass (COG) bonding process for liquid crystal display (LCD) driver chip packaging. The experimental results showed that the thickness of Al overlayer on PI core of the bump, the location of pin contact, and the bump configuration affect bump probing testability. The bump with type IV configuration prepared in this work exhibited excellent probing testability when its Al overlayer thickness exceeded 0.8 μm. We further employed Taguchi method to identify the optimum COG bonding parameters for the Al/PI composite bump. The four bonding parameters, bonding temperature, bonding time, bonding pressure and thickness of Al overlayer are identified as 180° C, 10 s, 800 kgf/cm2 and 1.4 μm, respectively. The optimum bonding condition was applied to subsequent COG bonding experiments on glass substrates containing Al pads or indium tin oxide (ITO) pads. From the results of resistance measurement along with a series of reliability tests, Al pad is found to be a good substrate bonding pad for Al/PI bump to COG process. Excellent contact quality was observed when the bumps had Al overlayer thickness over 1.1 μm. As to the COG specimens with substrate containing ITO pads, high joint resistance suggested that further contact quality refinement is necessary to realize their application to COG process View full abstract»

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Aims & Scope

IEEE Transactions on Components and Packaging Technologies publishes research and applications articles on the modeling, building blocks, technical infrastructure, and analysis underpinning electronic, photonic, MEMS and sensor packaging.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Koneru Ramakrishna
Freescale Semiconductor, Inc.