Scheduled System Maintenance:
On May 6th, single article purchases and IEEE account management will be unavailable from 8:00 AM - 5:00 PM ET (12:00 - 21:00 UTC). We apologize for the inconvenience.
By Topic

Electron Device Letters, IEEE

Issue 6 • Date June 2001

Filter Results

Displaying Results 1 - 15 of 15
  • A 0.15-μm 60-GHz high-power composite channel GaInAs/InP HEMT with low gate current

    Publication Year: 2001 , Page(s): 257 - 259
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    This letter presents recent improvements and experimental results provided by GaInAs/InP composite channel high electron mobility transistors (HEMT). The devices exhibit good dc and rf performance. The 0.15-μm gate length devices have saturation current density of 750 mA/mm at V/sub GS/=+0 V. The Schottky characteristic is a typical reverse gate-to-drain breakdown voltage of -8 V. Gate current issued from impact ionization has been studied in these devices, in the first instance, versus drain extension. At 60 GHz, an output power of 385 mW/mm has been obtained in such a device with a 5.3 dB linear gain and 41% drain efficiency which constitutes the state-of-the-art. These results studied are the first reported for a composite channel Al/sub 0.65/In/sub 0.35/As/Ga/sub 0.47/In/sub 0.53/As/InP HEMT on an InP substrate. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-quality ultrathin (1.6 nm) nitride/oxide stack gate dielectrics prepared by combining remote plasma nitridation and LPCVD technologies

    Publication Year: 2001 , Page(s): 260 - 262
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB) |  | HTML iconHTML  

    Ultrathin nitride/oxide (N/O) gate dielectric stacks with equivalent oxide thickness of 1.6 nm have been fabricated by combining remote plasma nitridation (RPN) and low pressure chemical vapor deposition (LPCVD) technologies. NMOSFETs with these gate stacks exhibit good interface properties, improved subthreshold characteristics, low off-state currents, enhanced reliability, and about one order of magnitude reduction in gate leakage current to their oxide counterparts. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Leakage mechanism in Cu damascene structure with methylsilane-doped low-K CVD oxide as intermetal dielectric

    Publication Year: 2001 , Page(s): 263 - 265
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    This letter investigates the leakage mechanism in the Cu damascene structure with methylsilane-doped low-k CVD organosilicate glass (OSG) as the intermetal dielectric (IMD). The leakage between Cu lines was found to be dominated by the Frenkel-Poole (F-P) emission in OSG for the structure using a 50-nm SiC etching stop layer (ESL). In the structure using a 50-nm SiN ESL, the leakage component through SiN also made a considerable contribution to the total leakage in addition to the bulk leakage from trapped electrons in OSG. An appropriate ESL of sufficient thickness is essential to reduce the leakage for application to a Cu damascene integration scheme. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Experimental demonstration of a silicon carbide IMPATT oscillator

    Publication Year: 2001 , Page(s): 266 - 268
    Cited by:  Papers (10)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (96 KB) |  | HTML iconHTML  

    Silicon carbide (SiC) is an excellent material for high-power and high-frequency applications because of its high critical field, high electron saturation velocity, and high thermal conductivity. In this letter, we report the first experimental demonstration of microwave oscillation in 4H-SiC impact-ionization-avalanche-transit-time (IMPATT) diodes. The prototype devices are single-drift diodes with a high-low doping profile. DC characteristics exhibit hard, sustainable avalanche breakdown, as required for IMPATT operation. Microwave testing is performed in a reduced-height waveguide cavity. Oscillations are observed at 7.75 GHz at a power level of 1 mW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-performance low-temperature poly-Si TFTs crystallized by excimer laser irradiation with recessed-channel structure

    Publication Year: 2001 , Page(s): 269 - 271
    Cited by:  Papers (14)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (121 KB) |  | HTML iconHTML  

    High-performance low-temperature poly-Si (LTPS) thin-film transistors (TFTs) have been fabricated by excimer laser crystallization (ELC) with a recessed-channel (RC) structure. The TFTs made by this method possessed large longitudinal grains in the channel regions, therefore, they exhibited better electrical characteristics as compared with the conventional ones. An average field-effect mobility above 300 cm/sup 2//V-s and on/off current ratio higher than 10/sup 9/ were achieved in these RC-structure devices. In addition, since grain growth could be artificially controlled by this method, the device electrical characteristics were less sensitive to laser energy density variation, and therefore the uniformity of device performance could be improved. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High channel mobility in normally-off 4H-SiC buried channel MOSFETs

    Publication Year: 2001 , Page(s): 272 - 274
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (60 KB) |  | HTML iconHTML  

    We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500/spl deg/C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10/sup 17/ cm/sup -3/, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm2/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Spiral inductors on Si p/p/sup +/ substrates with resonant frequency of 20 GHz

    Publication Year: 2001 , Page(s): 275 - 277
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (119 KB) |  | HTML iconHTML  

    Porous Si of up to 200 μm in thickness has been used to fabricate high-performance spiral inductors on heavily doped Si substrates (0.007 /spl Omega/-cm). Spiral inductors with L/spl sim/5.7 nH are fabricated demonstrating Qmax/spl sim/29 at 7 GHz and f/sub r/>20 GHz. The resonant frequency (f/sub r/) increases with increasing porous Si thickness and saturates beyond 120 μm. A corresponding decrease in total capacitance is observed. Qmax increases monotonically with porous Si layer thickness to beyond 200 μm. For inductors with a smaller footprint, Qmax begins to saturate at less than 100-μm thick porous Si. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Proposal of a partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET for deep sub-0.1-μm channel regime

    Publication Year: 2001 , Page(s): 278 - 280
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (74 KB) |  | HTML iconHTML  

    This letter proposes a new device structure which is called the "partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET." The PGP SOI MOSFET minimizes the short-channel effect (SCE) compared to the conventional single-gate (SG) SOI MOSFET because the gate-induced field in the SOI layer is held high by the PGP region. This results in a lower stand-by leakage current. The PGP SOI MOSFET also shows much better switching performance and extremely high analog performance because of its smaller parasitic capacitance compared to the conventional ground-plane (GP) device. Thus, it is shown that the PGP SOI MOSFET is a promising candidate for future deep-sub-0.1-μm mixed-mode LSIs. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An improved formula for the determination of the polysilicon doping

    Publication Year: 2001 , Page(s): 281 - 283
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB) |  | HTML iconHTML  

    This letter describes an improved formula for the extraction of the polysilicon doping from the C-V characteristic of MOS transistors. Analytical approximations are presented for the inversion layer contribution, which was neglected in previous work. The new approach returns an estimate error smaller than 10% when the full substrate and poly quantization are accounted for. Practical application to experimental data is also addressed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The effect of fluorine from BF2 source/drain extension implants on performance of PMOS transistors with thin gate oxides

    Publication Year: 2001 , Page(s): 284 - 286
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (61 KB) |  | HTML iconHTML  

    Boron penetration from the gate electrode into the Si substrate presents a significant problem in advanced PMOS device fabrication. Boron penetration, which causes a degradation of many transistor parameters, is further enhanced when BF2 is used to dope the gate electrode. It is known that pile-up of fluorine from the BR gate implant at the polysilicon/gate oxide interface is responsible for the enhanced boron penetration. However, no reports have been made that address enhanced boron penetration due to fluorine from the source/drain (S/D) implants. It is shown here that fluorine from the S/D extension implants is also a significant problem, degrading transistor performance for gate oxide thickness less than 27 /spl Aring/ and gate lengths less than 0.5 μm. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling

    Publication Year: 2001 , Page(s): 287 - 289
    Cited by:  Papers (58)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (64 KB) |  | HTML iconHTML  

    This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into small unit cells along its width, each unit cell assumes a constant gate length (i.e., cell's width is small compared to LER spatial frequency). An analytical model is used to represent saturated threshold voltage dependency on the unit cell's gate length. Using this technique, an efficient and accurate model for LER effects (through V/sub ts/ variations) on off-state leakage and drive current is proposed and experimentally validated using 193 and 248 nm lithography for devices with 80-nm nominal gate lengths. Assuming that the deviation from the ideal 0-LER case remains constant from generation to generation, the model predicts that 3 nm or less LER is required for 50-60-nm state-of-the-art devices in the 0.1-μm technology node. Based on data presented, we suggest that the LER requirement for this technology node is attainable with an alternated phase-shift type of patterning process. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A hydrogen-transport-based interface-trap-generation model for hot-carrier reliability prediction

    Publication Year: 2001 , Page(s): 290 - 292
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (48 KB)  

    Hot-carrier-induced interface-trap generation in n-channel MOSFETs is known to be related to hydrogen-mediated processes. We present a model for interface-trap generation based on release and transport of mobile hydrogen in the gate and sidewall oxides by injected carriers and its interactions with defect-precursors at the Si-SiO/sub 2/ interface. Simulations based on this model are able to predict supply voltage, channel length, and process dependence of the rate of interface-trap generation in n-channel MOSFETs. This approach helps reduce empiricism and technology dependence usually associated with conventional hot-carrier lifetime prediction methods. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the mobility versus drain current relation for a nanoscale MOSFET

    Publication Year: 2001 , Page(s): 293 - 295
    Cited by:  Papers (95)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (40 KB) |  | HTML iconHTML  

    The dependence of the linear and saturated drain current of a nanoscale MOSFET on the near-equilibrium, inversion layer mobility of a long-channel device from the same technology is examined. Simple expressions developed from a scattering theory of the MOSFET provide a quantitative relation between the long-channel mobility and the short-channel drain current. The theory explains the commonly observed mobility-dependence of the linear and saturated drain currents in present-day deep submicron MOSFETs, and the results can be extrapolated all the way to the ballistic limit. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New physics-based analytic approach to the thin-oxide breakdown statistics

    Publication Year: 2001 , Page(s): 296 - 298
    Cited by:  Papers (99)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (127 KB) |  | HTML iconHTML  

    A new analytic cell-based approach to the modeling of the oxide breakdown statistics is presented. The new model has the same predictive power as the standard percolation approach and the advantage of providing simple analytic results. The scaling with oxide thickness of the Weibull slope and the mean critical density of defects at breakdown are accounted for correctly. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An on-chip temperature sensor by utilizing a MOS tunneling diode

    Publication Year: 2001 , Page(s): 299 - 301
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (72 KB) |  | HTML iconHTML  

    A simple metal-oxide-semiconductor (MOS) tunneling diode was demonstrated for application to an integrated temperature sensor. The MOS diode equipped with a 21-/spl Aring/ oxide was biased inversely at 1.8 V to monitor its substrate temperature through gate current. The gate current increased more than 700 times when the diode was heated from 20 to 110/spl deg/C. An exponential fitting curve correlated the gate current and the substrate temperature. Moreover, characteristics of the diode were analyzed though C-V and I/sub 1.8 V/-n/sub i/ curves. The good temperature response of the MOS tunneling diode might be useful in self-diagnosis or self-protection IC applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Amitava Chatterjee