# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

## Filter Results

Displaying Results 1 - 12 of 12
• ### A realistic fault model and test algorithms for static random access memories

Publication Year: 1990, Page(s):567 - 572
Cited by:  Papers (156)  |  Patents (16)
| |PDF (552 KB)

Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the f... View full abstract»

• ### Multiple distributions for biased random test patterns

Publication Year: 1990, Page(s):584 - 593
Cited by:  Papers (64)  |  Patents (1)
| |PDF (716 KB)

The test of integrated circuits by random patterns is very attractive, since no expensive test pattern generation is necessary and tests can be applied with a self-test technique or externally using linear feedback shift registers. Unfortunately, not all circuits are random-testable, because either the fault coverage is too low or the required test length too large. In many cases the random test l... View full abstract»

• ### Testability analysis of analog systems

Publication Year: 1990, Page(s):573 - 583
Cited by:  Papers (38)
| |PDF (1040 KB)

A method is presented to analyze the testability of both linear and nonlinear analog systems. It combines a rank-test algorithm with statistical methods. The algorithm will find sets of dependent parameters and determine whether it is possible to calculate a certain parameter with sufficient accuracy. it also determines a subset of appropriate measurements if redundant measurements are present View full abstract»

• ### DVLASIC: catastrophic fault yield simulation in a distributed processing environment

Publication Year: 1990, Page(s):655 - 664
| |PDF (1060 KB)

Simulation of local process disturbances is a computationally intensive task. The VLASIC (VLSI LAyout Simulation for Integrated Circuits) catastrophic-fault yield simulator uses a Monte Carlo method that often requires tens of CPU hours to perform a simulation. In order to reduce the simulation time, DVLASIC, the distributed-environment version developed by the authors, achieves a speedup of 13.3 ... View full abstract»

• ### Continuous signature monitoring: low-cost concurrent detection of processor control errors

Publication Year: 1990, Page(s):629 - 641
Cited by:  Papers (84)  |  Patents (3)
| |PDF (1296 KB)

A low-cost approach to concurrent detection of processor control errors is presented that uses a simple hardware monitor and signatures embedded into the executing program. Existing signature-monitoring techniques detect a large portion of processor control errors at a fraction of the cost of duplication. Analytical methods developed in this study show that the new approach, continuous signature m... View full abstract»

• ### Application of scan hardware and software for debug and diagnostics in a workstation environment

Publication Year: 1990, Page(s):612 - 620
Cited by:  Patents (4)
| |PDF (800 KB)

An architecture for implementing scan technology for test and debug in a state-of-the-art workstation is described. Architectural features include controlling the scan and clock functions from a single resource that can also perform LFSR (linear feedback shift register) based pseudorandom testing and test result compression via signature capture. Operations of the scan subsystem are controlled fro... View full abstract»

• ### Hierarchical test generation using precomputed tests for modules

Publication Year: 1990, Page(s):594 - 603
Cited by:  Papers (109)
| |PDF (872 KB)

A novel test generation technique for large circuits with high fault coverage requirements is described. The technique is particularly appropriate for circuits designed by silicon compilers. Circuit modules and signals are described at a high descriptive level. Test data for modules are described by predefined stimulus/response packages that are processed symbolically using techniques derived from... View full abstract»

• ### Defensive programming' in the rapid development of a parallel scientific program

Publication Year: 1990, Page(s):665 - 669
Cited by:  Papers (1)  |  Patents (1)
| |PDF (572 KB)

A set of programming techniques which can reduce the time required to develop scientific programs is presented. Subroutines are designed to allow every execution path to be tested independently. Checksums are used to compress arrays and groups of variables without losing meaningful debugging information. Invariance assertions on checksums are used to detect incorrect behavior of a program at a pla... View full abstract»

• ### Estimation of maximum currents in MOS IC logic circuits

Publication Year: 1990, Page(s):642 - 654
Cited by:  Papers (64)  |  Patents (2)
| |PDF (1188 KB)

The authors deal with estimating currents in nMOS/CMOS IC logic circuits at three levels of hierarchies: gate level, macro level, and power/ground distribution level. Models are developed for estimating currents in a macro-cell (macro) in response to input excitations. Algorithms are developed to estimate the maximum current requirement for a macro and to identify the input excitation at which the... View full abstract»

• ### Experiences with concurrent fault simulation of diagnostic programs

Publication Year: 1990, Page(s):621 - 628
Cited by:  Papers (1)
| |PDF (808 KB)

A methodology is presented for fault simulation of a system level diagnostic program involving large models (50000 to 200000 gates) and long test sequences. The accuracy of memory models and the interplay of fault insertion and fault selection with diagnostic program development are topics covered. It also details observation and statistical methods and tools used to investigate the operation of ... View full abstract»

• ### Easily testable PLA-based finite state machines

Publication Year: 1990, Page(s):604 - 611
Cited by:  Papers (15)
| |PDF (764 KB)

An outline is presented of a synthesis procedure that, beginning from a state transition graph (STG) description of a sequential machine, produces an optimized easily testable programmable logic array (PLA) based logic implementation. Previous approaches to synthesizing easily testable sequential machines have concentrated on the stuck-at-fault model; for PLAs, an extended fault model called the c... View full abstract»

• ### SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts

Publication Year: 1990, Page(s):669 - 674
Cited by:  Papers (3)  |  Patents (14)
| |PDF (924 KB)

Locating the geometrical features causing shorts is often the most vexing problem faced during the layout verification process. A description is given of an interactive CAD tool called Shortfinder that enables the user to find VLSI layout errors resulting in electrical shorts between complex nets quickly and with minimal effort. This is accomplished by displaying a cycle-free shortest electrical p... View full abstract»

## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu