Notice
There is currently an issue with the citation download feature. Learn more

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • May 2001

Filter Results

Displaying Results 1 - 13 of 13
  • Guest editors' introduction

    Publication Year: 2001, Page(s):569 - 570
    Request permission for commercial reuse | PDF file iconPDF (25 KB) | HTML iconHTML
    Freely Available from IEEE
  • Aggressor alignment for worst-case crosstalk noise

    Publication Year: 2001, Page(s):612 - 621
    Cited by:  Papers (40)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (179 KB) | HTML iconHTML

    In this paper, we study signal alignment resulting in maximum peak interconnect coupling noise. We consider three cases. In the first one, we assume that arbitrary arrival times of input signals are feasible. In the second case, we assume that timing windows are given for each aggressor input. The victim is quiet for the above two cases. In the third case, the victim net has a propagated noise fro... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Handling soft modules in general nonslicing floorplan using Lagrangian relaxation

    Publication Year: 2001, Page(s):687 - 692
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    In the early stage of floorplan design, many modules have large flexibilities in shape (soft modules). Handling soft modules in general nonslicing floorplan is a complicated problem. Many previous works have attempted to tackle this problem using heuristics or numerical methods, but none of them can solve it optimally and efficiently. In this paper, we show how this problem can be solved optimally... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • DUNE-a multilayer gridless routing system

    Publication Year: 2001, Page(s):633 - 647
    Cited by:  Papers (30)  |  Patents (63)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB) | HTML iconHTML

    Advances of very large scale integration technologies present two challenges for routing problems: (1) the higher integration of transistors due to shrinking of featuring size and (2) the requirement for off-grid routing due to the variable-width variable-spacing design rules imposed by optimization techniques. In this paper, we present a multilayer gridless detailed routing system for deep submic... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Routability-driven repeater block planning for interconnect-centric floorplanning

    Publication Year: 2001, Page(s):660 - 671
    Cited by:  Papers (15)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB) | HTML iconHTML

    In this paper, we present a repeater block planning algorithm for interconnect-centric floorplanning. We introduce the concept of independent feasible regions for repeaters and derive an analytical formula for their computation. We develop a routability-driven repeater clustering algorithm to perform repeater block planning based on iterative deletion. The goal is to obtain a high-quality solution... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Buffer minimization in pass transistor logic

    Publication Year: 2001, Page(s):693 - 697
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB) | HTML iconHTML

    With shrinking feature sizes and increasing transistor counts on chips, demands for higher speed and lower power make it necessary to look for alternative design styles that offer better performance than static complementary metal-oxide-semiconductors. Among them, pass transistor logic (PTL) is of great promise. Since delay in a transistor chain is quadratically proportional to the number of trans... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Toward accurate models of achievable routing

    Publication Year: 2001, Page(s):648 - 659
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Models of achievable routing, i.e., chip wireability, rely on estimates of available and required routing resources. Required routing resources are estimated from placement or (a priori) using wire length estimation models. Available routing resources are estimated by calculating a nominal “supply” then take into account such factors as the efficiency of the router and the impact of vi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pseudopin assignment with crosstalk noise control

    Publication Year: 2001, Page(s):598 - 611
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB) | HTML iconHTML

    This paper presents a new pseudopin assignment (PPA) algorithm with crosstalk noise control in multilayer gridless general-area routing. We propose a two-step approach that considers obstacles and minimizes the weighted sum of total wire length and the estimated number of vias under crosstalk noise constraints. We test our algorithms on a set of MCM examples and a set of standard-cell examples. Wi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Critical area computation for missing material defects in VLSI circuits

    Publication Year: 2001, Page(s):583 - 597
    Cited by:  Papers (22)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    We address the problem of computing critical area for missing material defects in a circuit layout. The extraction of critical area is the main computational problem in very large scale integration yield prediction. Missing material defects cause open circuits and are classified into breaks and via blocks. Our approach is based on the L ∞ medial axis of polygons and the weighted L... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hybrid dynamic/quadratic programming algorithm for interconnect tree optimization

    Publication Year: 2001, Page(s):680 - 686
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    We present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing in this paper. Both wire widths and buffer sizes are chosen from user-defined discrete sets. Our algorithm integrates the quadratic programming approach for handling a wire branch into the dynamic programming (DP) framework. Our experimental results show that our hybrid dyna... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • RC delay metrics for performance optimization

    Publication Year: 2001, Page(s):571 - 582
    Cited by:  Papers (77)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    For performance optimization tasks such as floorplanning, placement, buffer insertion, wire sizing, and global routing, the Elmore resistance-capacitance (RC) delay metric remains popular due to its simple closed form expression, fast computation speed, and fidelity with respect to simulation. More accurate delay computation methods are typically central processing unit intensive and/or difficult ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Global routing by new approximation algorithms for multicommodity flow

    Publication Year: 2001, Page(s):622 - 632
    Cited by:  Papers (50)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    We show how the new approximation algorithms by Garg and Konemann with extensions due to Fleischer for the multicommodity flow problem can be modified to solve the linear programming relaxation of the global routing problem. Implementation issues to improve the performance, such as a discussion of different functions for the dual variables and how to use the Newton method as an additional optimiza... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wire packing - a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution

    Publication Year: 2001, Page(s):672 - 679
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB) | HTML iconHTML

    By focusing on chip-wide slices of the global routing grid, making a few mild geometric assumptions about layer use, and suitably abstracting pin details, we derive an efficient integer linear programming formulation for track/layer assignment. The key technical insight is to model all constraints both geometric and crosstalk - as cliques in an appropriate conflict graph; these cliques can be extr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu