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Electron Devices, IEEE Transactions on

Issue 5 • Date May 2001

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Displaying Results 1 - 25 of 34
  • Changes in the Editorial Board

    Page(s): 829
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    Freely Available from IEEE
  • Body bias dependence of 1/f noise in NMOS transistors from deep-subthreshold to strong inversion

    Page(s): 999 - 1001
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    Dependence of 1/f noise on the body-to-source junction bias voltages (VBS) between -2.5 and 0.5 V for 0.25-μm NMOS transistors is reported. In subthreshold, 1/f noise is reduced by about one order of magnitude, when the body-to-source junction is forward biased by 0.5 V (VBS) compared to that for VBS=0 V, which is due to increased depletion layer capacitance as well as possibly due to an increased average distance between oxide traps and carriers caused by the forward bias. On the contrary, in strong inversion, 1/f noise remains almost constant for the entire VBS range View full abstract»

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  • Effective channel length and external series resistance models of scaled LDD pMOSFETs operating in a Bi-MOS hybrid-mode environment

    Page(s): 1001 - 1004
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    The effective channel length Leff and total external series resistance RTOText of deep submicron lightly doped drain (LDD) pMOSFETs, operating in a Bi-MOS hybrid-mode environment, have been modeled as functions of bias and temperature. The accuracy of the device threshold voltage used in the Leff and RTOText extraction routine is discussed. The proposed models have been verified for temperature ranging from 223 K to 398 K and source-to-body voltage VSB>0 V conditions View full abstract»

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  • Optical characteristics of silicon semiconductor bridges under high current density conditions

    Page(s): 852 - 857
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    The optical emission spectra (180-700 nm) of plasma produced by a semiconductor bridge (SCB) with aluminum or tungsten electrodes have been measured and analyzed. The spatially and temporally resolved emission spectra of the SCB device have provided insights into the dynamic discharge of the bridge. The plasma electron temperature of the SCB device was measured using the comparison of the continuum emission of the bridge with the calculated optical emission spectra for a gray body source. Measured electron temperatures in the plasma produced by the bridges are related to the capacitor discharging voltage. The best estimates indicate that 4100-5500 K was measured for Al-electrode SCB device and 5650-6000 K for W-electrode SCB device View full abstract»

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  • Excess currents induced by hot hole injection and FN electron injection in thin SiO2 films

    Page(s): 868 - 873
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    The behavior of excess currents induced by Fowler-Nordheim electron injection stress (FN electron injection) has been investigated for 6.0-nm oxides. Excess currents are induced by FN electron injection in 6.0-nm oxides together with positive charges being induced in it. To clarify the role of hole injection in FN electron injection, the behavior of excess currents induced by substrate hot hole injection has also been investigated in 6.0-nm oxides. The leakage behavior after hot hole injection is the same as FN electron injection. The excess currents induced both by the FN electron injection and by the substrate hot hole injection are due to trap-assisted tunneling and field enhancement at the cathode due to the positive trapped charge. The charge centroid of the positive charges induced by both stresses are located 3.0 nm from the Si/SiO2 interface which is at the center of 6.0-nm oxide. The excess currents induced by hot hole injection and FN electron injection are caused by traps in SiO2 films produced by injected holes from the anode View full abstract»

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  • Analysis of the DCIV peaks in electrically stressed pMOSFETs

    Page(s): 913 - 920
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    This paper presents the effects of Fowler-Nordheim (FN) and hot-carrier (HC) stress in the direct-current current voltage (DCIV) measurements. The effect of interface trapped charge on DCIV curves is reported. Stress-induced oxide charge shifts the DCIV peaks, while stress-induced interface trapped charge causes a spread in the DCIV peaks. It is found that under HC stress, when the absolute value of stress gate voltage changes from low to high, the interface trap spatial location moves from the drain region to the channel region. It is inferred that the generation of oxide charge in the drain region is a two-step process. For short stress times, electrons mainly fill the process-induced neutral oxide traps, while for long stress times, electrons fill the stress created electron traps View full abstract»

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  • A new model of gate capacitance as a simple tool to extract MOS parameters

    Page(s): 935 - 945
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    This paper tackles the difficult task to extract MOS parameters by a new model of the gate capacitance that takes into account both poly-Si depletion and charge quantization and includes temperature effects. A new fast and iterative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, and poly-Si doping) and oxide field, surface potentials at the Si/SiO2 and at the poly-Si/SiO2 interfaces. Its effectiveness will be demonstrated by comparing oxide field and oxide thickness to those extracted by other methods proposed in the literature. Moreover, these methods are critically reviewed and we suggest improvements to reduce their errors. The agreement between CV simulation and experimental data is good without the need of any free parameter to improve the fitting quality for several gate and substrate materials combinations. Finally, a simple law to estimate substrate and poly-Si doping in n+/n + MOS capacitors from CV curves is proposed View full abstract»

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  • Schottky barrier depletion modification-a source of output conductance in submicron GaAs MESFETs

    Page(s): 830 - 834
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    This investigation offers a new explanation for the output conductance in submicron GaAs MESFET characteristics. Prior to the avalanche breakdown a sharp rise in the reverse Schottky barrier current, Igs is observed at a potential where drain-to-source current, Ids saturates. This could be attributed to the fact that after the onset of current saturation there is an increase in the effective channel height of the device as a function of drain-to-source voltage, Vds. Experimental data suggest that by increasing V ds, there are more unbalanced positive ionic charges in the gate depletion toward the drain-side of the Schottky barrier. The electric field lines originated by these uncompensated charges induce an opposite charge density in the gate electrode. This modifies the gate biasing and hence the Schottky barrier depletion. As a result there is a wider available channel crossection for the flow of Ids(Vds) and consequently the current-voltage (I-V) characteristics exhibit a positive slope after Vds saturation View full abstract»

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  • Polysilicon TFT technology for active matrix OLED displays

    Page(s): 845 - 851
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    The integration of active matrix polysilicon TFT technology with organic light emitting diode (OLED) displays has been investigated with the goal of producing displays of uniform brightness. This work identifies and addresses several process integration issues unique to this type of display which are important in achieving bright and uniform displays. Rapid thermal processing has been incorporated to achieve uniform polysilicon microstructure, along with silicides to reduce parasitic source and drain series resistance. Using these processes, TFT drain current nonuniformity has been reduced below 5% for 90% of the devices. This work also introduces transition metals to produce low resistance contacts to ITO and to eliminate hillock formation in the aluminum metallization. These processes, along with spin on glasses for planarization, have been used to produce functional active matrix arrays for OLED displays. The final array pixel performance is also presented View full abstract»

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  • Gate-induced drain leakage current enhanced by plasma charging damage

    Page(s): 1006 - 1008
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    Correlation between gate-induced drain leakage (GIDL) current I GIDL and plasma charging damage is investigated for p-MOSFETs. IGIDL and maximum charge pumping current show the same trend as a function of antenna area ratio (AAR) and cell location. Enhancement of IGIDL is mainly attributed to the increase of Si/SiO2 interface traps generated in the plasma processes and is not related to the small amount of trapped charge in the oxide View full abstract»

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  • Bipolar transistor selected P-channel flash memory cell technology

    Page(s): 863 - 867
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    A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory View full abstract»

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  • Patterning sub-30-nm MOSFET gate with i-line lithography

    Page(s): 1004 - 1006
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    We have investigated two process techniques: resist ashing and oxide hard mask trimming. A combination of ashing and trimming produces sub-30-nm MOSFET gates. These techniques require neither specific equipment nor materials. These can be used to fabricate experimental devices with line width beyond the limit of optical lithography or high-throughput e-beam lithography. They provide 25-nm gate patterns with i-line lithography and sub-30-nm pattern with e-beam lithography. A 40-nm gate channel length nMOSFET is demonstrated View full abstract»

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  • Self-consistent simulation of the spatial-harmonic magnetron with cold secondary-emission cathode

    Page(s): 993 - 998
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    A self-consistent mathematical model of the spatial-harmonic magnetron (SHM), with cold secondary-emission cathode is proposed for investigating steady-state processes. Characteristic features of modeling space charge effects, secondary emission, and nonlinear electron-wave interaction are described. Illustrative examples of simulations are given in order to show peculiarities of the operation of the SHM as compared to conventional magnetrons. Multi-stable states of the magnetron are described. Results of simulations are compared with experimental data for an 8-mm-wave magnetron View full abstract»

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  • Low-frequency noise in TFSOI lateral n-p-n bipolar transistors

    Page(s): 956 - 965
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    Low-frequency (1/f) noise is characterized as a function of base current density (JB) on thin-film-silicon-on-insulator (TFSOI) lateral bipolar transistors. In the low injection region of operation, the noise power spectral density was proportional to JB 1.8 for JB<0.4 μA/μm2, which suggest that the noise in these devices is primarily dominated by a uniform distribution of noise sources across the emitter-base area. However in the high current region of operation (JB>0.4 μm2), the noise bias dependence shifts to JB 1.2, indicating current crowding effects, alter the contribution of noise sources near the extrinsic base link region of the device. In addition to the expected 1/f noise and shot noise, we have observed a bias dependent generation-recombination (Gm) noise source in some of the devices. This G/R noise is correlated to random-telegraph-signal (RTS) noise resulting from single trapping centers, located at or near the spacer oxide and/or the Si to SIMOX interface, which modulate the emitter-base space charge region View full abstract»

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  • Reliability of thin oxides grown on deuterium implanted silicon substrate

    Page(s): 1015 - 1016
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    We have investigated the reliability of gate oxide with deuterium incorporated at the Si/SiO2 interface through low energy ion implantation into the silicon substrate before thin gate oxide growth. Deuterium implantation at a dose of 1×1014/cm2 at 25 keV showed improved breakdown characteristics. Charge-to-breakdown seems to correlate well with the interface state density measured by the conductance method View full abstract»

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  • Characteristics of p-channel Si nano-crystal memory

    Page(s): 874 - 879
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    In this work, the feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. By comparing the programming characteristics of devices with nano-crystals and devices without nano-crystals, the role of dots as storage node is presented. The programming and erasing mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. In case of erasing, the electron tunneling occurs from either the conduction band or the valence band. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time View full abstract»

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  • 1/f noise in CMOS transistors for analog applications

    Page(s): 921 - 927
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    Noise measurements of the 1/f noise in PMOS and NMOS transistors for analog applications are reported under wide bias conditions ranging from subthreshold to saturation. Two “low noise” CMOS processes of 2 μm and 0.5 μm technologies are compared and it is found that the more advanced process, with 0.5 μm technology, exhibits significantly reduced 1/f noise, due to optimized processing. The input referred noise and the power spectral density (PSD) of the drain current 1/f noise are modeled in saturation as well as in subthreshold and are compared with the common empirical approaches such as the SPICE models. The results of this study are useful to the design and modeling of 1/f noise of CMOS analog circuits View full abstract»

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  • Vertical N-channel MOSFETs for extremely high density memories: the impact of interface orientation on device performance

    Page(s): 897 - 906
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    We investigate vertical n-channel MOSFETs fabricated at the sidewalls of etched trenches. In general, these sidewalls can be nonplanar and incorporate different crystallographic orientations. Therefore, it is necessary to involve models for a variety of interface orientations in order to describe scaled-down vertical devices. However, the crystallographic orientation of the interface has a strong impact on crucial device parameters such as gate oxide thickness, carrier mobility, and interface trap density. For the first time, in this work a complete set of these parameters is investigated systematically for a wide range of different crystallographic orientations. Based on these parameters, the modeling of vertical MOSFETs featuring a cylindrical geometry is demonstrated and verified by measurements. Furthermore, differences observed between vertical and planar devices of equal parameters are deduced from interface properties related to the orientation of the sidewall View full abstract»

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  • Experimental evidence of interface-controlled mechanism of quasi-breakdown in ultrathin gate oxide

    Page(s): 1010 - 1013
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    The quasi-breakdown (QB) mechanism of thin gate oxide was investigated through observation of defects generation during stress. It has been found that the amount of interface traps reaches the same critical value at the onset point of QB regardless of stress conditions, implying that QB in thin oxide is triggered by a critical amount of interface traps View full abstract»

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  • A GaAs solar cell with an efficiency of 26.2% at 1000 suns and 25.0% at 2000 suns

    Page(s): 840 - 844
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    A GaAs solar cell without prismatic covers, with the highest efficiency known to the authors in the range of 1000-2000 suns for a single junction, is presented. Low temperature liquid phase epitaxy is used for its growth. In addition to improvements such as the achievement of a good quality material or a low contact resistance, this solar cell exhibits specific enhanced aspects. Among the most noticeable are: (1) an innovative design; (2) a double and gradual emitter layer; (3) a small size: 1 mm2, (4) a finger width of the front metal grid of 3 μm; and (5) a tailored ARC deposition based on a nondestructive and accurate AlGaAs window layer characterization. As a consequence, an efficiency of 26.2% at 1000 suns and 25.0% at 2000 suns AM1.5D (standard conditions) is achieved thanks mainly to a short-circuit current density at 1000 suns of 26.8 A/cm2 (and 53.6 A/cm2 at 2000 suns) with a simultaneous series resistance of 3 mΩ·cm2 View full abstract»

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  • Characterization of ultrathin oxynitride (18-21 A) gate dielectrics by NH3 nitridation and N2O RTA treatment

    Page(s): 907 - 912
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    In this paper, we developed a new method to grow robust ultrathin oxynitride (EOT=18 A) film with effective dielectric constant of 7.15. By NH3-nitridation of Si substrate, grown ultrathin Si3N4 With N2O annealing shows excellent electrical properties in terms of significant lower leakage current, very low bulk trap density and trap generation rate, and high endurance in stressing. In addition, this oxynitride film exhibits relatively weak temperature dependence due to a Fowler-Nordheim (FN) tunneling mechanism. This dielectric film appears to be promising for future ultralarge scale integrated (ULSI) devices View full abstract»

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  • A physically based relation between extracted threshold voltage and surface potential flat band voltage for MOSFET compact modeling

    Page(s): 1019 - 1021
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    Compact MOS models based on surface potential are now firmly established, but for practical applications there is no reliable link between measured values of threshold voltage and the flat-band voltage on which such models are based. This brief presents an analytical relationship which may be implemented in compact models to provide a reliable and accurate threshold parameter input. Results are compared with a conventional threshold voltage model for several SOI CMOS technologies. This technique has been developed for use with body-tied SOI transistors, and hence it can also be applied to bulk devices View full abstract»

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  • Current gain dependence on subcollector and etch-stop doping in InGaP/GaAs HBTs

    Page(s): 835 - 839
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    The DC current gain dependence of InGaP/GaAs heterojunction bipolar transistors (HBTs) on subcollector and etch-stop doping is examined. Samples of InGaP/GaAs HBTs having various combinations of subcollector doping and etch-stop doping are grown, and large area 60 μm×60 (μ) HBTs are then fabricated for DC characterization. It is found that the DC current gain has a strong dependence on the doping concentration in the subcollector and the subcollector etch-stop. Maximum gain is achieved when the subcollector is doped at 6~7×10 18 cm-3 while the subcollector etch-stop is doped either above 6×1018 cm-3 (current gain/sheet resistance ratio, β/Rb=0.435 at Ic=1 mA) or below 3.5×1017 cm-3 (β/Rb=0.426~0.438 at Ic=1 mA). The data show that it is not necessary to heavily dope the subcollector etch-stop to reduce the conduction barrier and to obtain high current gain. The high current gain obtained with the low InGaP etch-stop doping concentration is attributed to the reduction of the effective energy barrier thickness due to band bending at the heterojunction between the InGaP etch-stop and the GaAs subcollector. These results show that the β/Rb of InGaP/GaAs HBTs can improve as much as 69% with the optimized doping concentration in subcollector and subcollector etch-stop View full abstract»

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  • Isolation on Si wafers by MeV proton bombardment for RF integrated circuits

    Page(s): 928 - 934
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    This paper studies issues related with using high energy protons to create local semi-insulating silicon regions on IC wafers for device isolation and realization of high-Q IC inductors. Topics on two approaches, i.e., one using Al as the radiation mask and the other using proton direct-write on wafers were studied. It was shown that Al can effectively mask the proton bombardment of 15 MeV up to the fluence of 1017 cm-2. For the unmasking direct write of the proton bombardment, isolation in the silicon wafer can be achieved without damaging active devices if the proton fluence is kept below 1×1014 cm-2 with the substrate resistivity level chosen at 140 Ω-cm, or kept at 1×1015 cm -2 with the substrate resistivity level chosen at 15 Ω-cm. Under the above approaches, the 1 h-200°C thermal treatment, which is necessary for device final packaging, still gives enough high resistivity for the semi-insulating regions while recovering somewhat the active device characteristics. For the integrated passive inductor fabricated on the surface of the silicon wafer, the proton radiation improves its Q value View full abstract»

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  • Semiconductor transport simulation with the local iterative Monte Carlo technique

    Page(s): 946 - 955
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    In typical particle simulations applied to device problems, it is desirable to simulate regions having widely different carrier concentration with similar resolution of the energy distribution function. Standard Monte Carlo (MC) algorithms use variance reduction techniques to limit the statistical error in regions of low carrier density. Here, we describe an alternative approach, based on a local iterative MC algorithm, where the carrier distribution is calculated by an iterative application of short MC steps for test particles that represent the local density. The information obtained from the local MC procedure is used to compute directly the evolution of the energy distribution function from an initial distribution until a steady state is reached. This local iterative procedure treats the charge density, represented by the MC, with arbitrary weight, independently of the actual number of physical particles corresponding to a given density. In this way, the computation time is the same for low- or high-density regions, leading to a more efficient use of computational resources and uniform statistical error. The computation time can be reduced also by tabulating and using more than once the results from the local MC steps in the overall iteration process. While the local iterative MC approach does not have the generality of the standard MC technique, much faster calculations and greatly reduced statistical noise are possible when applied to steady-state problems. We present a number of simulation examples for silicon devices, which illustrate the capabilities of the approach View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology