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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 2 • Date Feb. 2001

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Displaying Results 1 - 15 of 15
  • Comments on "Comments on "A systematic approach for design of digit serial signal processing architectures

    Publication Year: 2001 , Page(s): 177 - 179
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (55 KB) |  | HTML iconHTML  

    In the above paper, [see ibid., vol. 47, p. 369-70, 2000] the authors have modified the nonrestoring square root algorithm (Q=/spl radic/A) and its architecture [see ibid., vol. 38, p.358-75, 1991] to give correct results. They claimed that the partial remainder (PR) should be kept as is rather than eliminating its MSB at each step of the algorithm. Since two bits of A are appended to PR at each s... View full abstract»

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  • Current-mode biquad with a minimum number of passive elements

    Publication Year: 2001 , Page(s): 221 - 222
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (64 KB)  

    This brief reports a current-mode LP, HP and BP filter which ideally exhibits zero input and very high output resistance. All active and passive sensitivities are no more than one half in magnitude. The filter employs a minimum number of passive elements, only two capacitors and two resistors, and two filter functions can simultaneously be realized View full abstract»

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  • An analysis of dynamic element matching flash digital-to-analog converters

    Publication Year: 2001 , Page(s): 205 - 213
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (288 KB)  

    Although many dynamic element matching (DEM) digital-to-analog converters (DACs) have identical architectures, analyses of DEM DACs have been specific to the DAC DEM algorithm or based on simulation results. In this paper, a commonly used flash DEM DAC architecture is analyzed. Using this analysis, a DEM DAC's mean integral nonlinearity (INL), variance of the LNL, output signal-to-distortion ratio... View full abstract»

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  • A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator

    Publication Year: 2001 , Page(s): 216 - 221
    Cited by:  Papers (47)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (196 KB)  

    A 900-MHz two-stage CMOS voltage-controlled ring oscillator (VCO) with good phase-noise performance is presented. Implemented in a 0.5-μm CMOS technology and at 2.5-V supply voltage, the VCO has a wide operating frequency range from 661.5 MHz to 1.27 GHz with a peak VCO gain (KVCO) of -630 MHz/V. At 900 MHz, the phase noise of the VCO is -105.5 dBc/Hz at 600-kHz frequency offset with... View full abstract»

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  • Second-order delta-sigma modulation with interfered reference

    Publication Year: 2001 , Page(s): 192 - 197
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (260 KB)  

    A delta-sigma (ΔΣ) modulator has been traditionally analyzed by assuming its reference to be constant, but practically the reference may be interfered and thus vary with time. For an interfered reference modulator, the performance of quantization noise is degraded by quantization noise leakage due to interfered feedback. In this paper, a systematic study for observing the behavior of a... View full abstract»

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  • Self-tested self-synchronization circuit for mesochronous clocking

    Publication Year: 2001 , Page(s): 129 - 140
    Cited by:  Papers (21)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (268 KB) |  | HTML iconHTML  

    In large-scale and high-speed systems, global synchronization has been commonly used to protect clocked I/O from data read failure caused by metastability. There are many drawbacks with global synchronization, which will approach its physical limit in the future as system clock frequency and system scale increase simultaneously. Mesochronous clocking overcomes these drawbacks, but without a proper... View full abstract»

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  • Design of adaptive envelope-constrained filters in the presence of impulsive noise

    Publication Year: 2001 , Page(s): 188 - 192
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (148 KB)  

    The problem of designing adaptive filters subject to output envelope constraints in the presence of impulsive noise at the input channel is investigated. Median smoothing is incorporated into the recently developed adaptive envelope-constrained filtering algorithms with a view to suppressing the effect of impulsive noise. It is demonstrated that the proposed adaptive filtering algorithms can provi... View full abstract»

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  • A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs

    Publication Year: 2001 , Page(s): 158 - 170
    Cited by:  Papers (11)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (344 KB)  

    A multibit ΔΣ analog-to-digital converter can achieve high resolution with a lower order modulator and lower oversampling ratio than a single-bit design. However, in a multihit ΔΣ modulator, quantization level errors in the internal multibit quantizer can limit the ΔΣ modulator's signal-to-noise-and-distortion and spurious-free dynamic range. For a CMOS Δ&... View full abstract»

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  • Some properties of the matrix exponential

    Publication Year: 2001 , Page(s): 213 - 215
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (112 KB)  

    We give a simple condition on a matrix A for which if the exponential matrix eA is diagonal, lower or upper triangular, then so is A. It is also shown that for diagonalizable A and any matrix B, eA and B commute if and only if A and B commute. These results are useful in problems in which knowledge about A has to be extracted from structural information about its exponential,... View full abstract»

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  • The discrete time wavelet transform: its discrete time Fourier transform and filter bank implementation

    Publication Year: 2001 , Page(s): 180 - 183
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (148 KB)  

    Viewing the discrete time wavelet transform DTWT[m,n] of a sampled signal s(nT) as a sequence in n, a closed-form expression is derived for its Discrete Time Fourier Transform (DTFT) D(m)(e) in terms of the DTFTs of the sampled mother wavelet ψ(nT) and sampled signal s(nT). Next, an expression is derived for the output Y(m)(e) of a fi... View full abstract»

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  • Boundary filters for size-limited paraunitary filter banks with maximum coding gain and ideal DC behavior

    Publication Year: 2001 , Page(s): 183 - 188
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (284 KB)  

    This paper presents boundary optimization techniques for the processing of arbitrary-length signals with paraunitary multirate filter banks. The boundary filters are designed to maximize the coding gain while providing an ideal DC behavior where all filters except the low-pass filters have zero mean. Moreover, solutions are presented that have similar frequency responses as the original subband fi... View full abstract»

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  • Semiparallel rank order filtering in analog VLSI

    Publication Year: 2001 , Page(s): 198 - 205
    Cited by:  Papers (9)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (204 KB)  

    This paper demonstrates two related techniques for spatially encoding rank in an unlimited array of analog inputs. During a particular read cycle, a single output of the array is low, indicating that the corresponding input holds the rank related to the current read cycle. Ranks are computed in succession, in decreasing order, and may not be skipped in the rank filtering process. Since a single ra... View full abstract»

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  • Analysis of 1/f noise in switched MOSFET circuits

    Publication Year: 2001 , Page(s): 151 - 157
    Cited by:  Papers (30)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    Analysis of 1/f noise in MOSFET circuits is typically performed in the frequency domain using the standard stationary 1/f noise model. Recent experimental results, however, have shown that the estimates using this model can be quite inaccurate especially for switched circuits. In the case of a periodically switched transistor, measured 1/f noise power spectral density (psd) was shown to be signifi... View full abstract»

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  • An all-digital built-in self-test for high-speed phase-locked loops

    Publication Year: 2001 , Page(s): 141 - 150
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (160 KB) |  | HTML iconHTML  

    We propose a new structural testing of phase-locked loops (PLLs) using charge-based frequency measurement BIST (CF-BIST) technique. The technique uses the existing charge-pump as the stimulus generator and the VCO/divide-by-N as the measuring device to reduce the area overhead. This approach performs simple dc-like charge injection tests, thus, it is suitable for high-speed PLL applications. Fault... View full abstract»

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  • Two-step quantization in multibit ΔΣ modulators

    Publication Year: 2001 , Page(s): 171 - 176
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (108 KB)  

    An architecture to simplify the circuit implementation of the internal analog-to-digital (A/D) converter in a ΔΣ modulator is proposed. The architecture is based on dividing the A/D conversion into two time steps, which makes the internal quantization feasible with much higher resolution than with conventional solutions. Furthermore, the time steps are interleaved so that the resolutio... View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope