IEE Proceedings - Software

Issue 1 • 2001

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Displaying Results 1 - 4 of 4
  • High-level Petri net for incremental analysis of object-oriented system requirements

    Publication Year: 2001, Page(s):11 - 18
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (788 KB)

    To complement the weakness of Petri nets in terms of naturalness, modularity, and reusability, high-level Petri nets with object concepts have been suggested. It is difficult to apply these nets to the requirement specification of object oriented software systems because of insufficient support for the object oriented concepts. A hierarchical object oriented Petri net (HOONet) is developed to comp... View full abstract»

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  • Introducing monitoring events to timed-CSP

    Publication Year: 2001, Page(s):19 - 29
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1068 KB)

    Timed-CSP is a process algebra designed to help in the modelling and analysis of real time concurrent systems. Timed-CSP can handle synchronisation events that require the cooperation of all the interested parties, and broadcasting events which do not require any cooperation from the environment. The paper argues that, still, there are scenarios that cannot be adequately modelled in timed-CSP, and... View full abstract»

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  • Evaluating composite events using shared trees

    Publication Year: 2001, Page(s):1 - 10
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (952 KB)

    Distributed and concurrent systems tend to generate large numbers of events which require further processing, such as filtering and establishment of co-relations, to become useful for human or automated managers. The work focuses on the detection of composite events defined through event expressions involving primitive events and some operators: Boolean conjunction and disjunction; sequence, repet... View full abstract»

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  • Hardware compilation for software engineers: an ATM example

    Publication Year: 2001, Page(s):31 - 42
    Cited by:  Papers (3)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1140 KB)

    Forthcoming technology such as single-chip RISC/FPGA combinations make hardware compilation, fast prototyping and FPGA replacement of ASICs all more likely. FPGAs have made a software-oriented approach to digital design feasible. Remaining obstacles to this approach are reviewed. The trade-offs between use of an HDL and a C-variant, Handel-C, for logic synthesis are considered, particularly with r... View full abstract»

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Aims & Scope

Published from 1997-2006, IEE Proceedings - Software included original contributions of interest to practitioners, researchers and managers who were engaged in software engineering. It covered all aspects of the software lifecycle, including design, development, implementation and maintenance.

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