By Topic

Software, IEE Proceedings -

Issue 1 • Date 2001

Filter Results

Displaying Results 1 - 4 of 4
  • Evaluating composite events using shared trees

    Publication Year: 2001 , Page(s): 1 - 10
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (952 KB)  

    Distributed and concurrent systems tend to generate large numbers of events which require further processing, such as filtering and establishment of co-relations, to become useful for human or automated managers. The work focuses on the detection of composite events defined through event expressions involving primitive events and some operators: Boolean conjunction and disjunction; sequence, repetition, and absolute, periodic and relative timer events. A concrete result of this work was the design and implementation of a general purpose event processing service (EPS) which may be used by monitoring applications to be informed about the occurrence of primitive and composite events. Composite events are commonly represented as trees where the leaf nodes represent primitive event types and the intermediate nodes represent any of the supported event operators. The main contribution of the work is the description of a method to process composite events that share common sub-expressions with other composite events. The EPS was implemented in Java within the framework of the Sampa project View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Introducing monitoring events to timed-CSP

    Publication Year: 2001 , Page(s): 19 - 29
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1068 KB)  

    Timed-CSP is a process algebra designed to help in the modelling and analysis of real time concurrent systems. Timed-CSP can handle synchronisation events that require the cooperation of all the interested parties, and broadcasting events which do not require any cooperation from the environment. The paper argues that, still, there are scenarios that cannot be adequately modelled in timed-CSP, and proposes an extension that would allow the modelling of more advanced communication mechanisms, such as multicasting View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-level Petri net for incremental analysis of object-oriented system requirements

    Publication Year: 2001 , Page(s): 11 - 18
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    To complement the weakness of Petri nets in terms of naturalness, modularity, and reusability, high-level Petri nets with object concepts have been suggested. It is difficult to apply these nets to the requirement specification of object oriented software systems because of insufficient support for the object oriented concepts. A hierarchical object oriented Petri net (HOONet) is developed to complement the weakness of the existing formalisms and formally define its syntax and semantics. A reachability analysis method is provided to check such behavioural properties as boundedness, liveness and persistence of the HOONet models. The HOONet provides incremental modelling and analysis of the requirements with the support of object oriented concepts View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hardware compilation for software engineers: an ATM example

    Publication Year: 2001 , Page(s): 31 - 42
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1140 KB)  

    Forthcoming technology such as single-chip RISC/FPGA combinations make hardware compilation, fast prototyping and FPGA replacement of ASICs all more likely. FPGAs have made a software-oriented approach to digital design feasible. Remaining obstacles to this approach are reviewed. The trade-offs between use of an HDL and a C-variant, Handel-C, for logic synthesis are considered, particularly with regard to programmability and the overall design process. A simple example in a likely application area, simulation/emulation of telecommunications switches, illustrates the analysis View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.