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Electron Device Letters, IEEE

Issue 4 • Date April 2001

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Displaying Results 1 - 11 of 11
  • Temperature dependent common emitter current gain and collector-emitter offset voltage study in AlGaN/GaN heterojunction bipolar transistors

    Publication Year: 2001 , Page(s): 157 - 159
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (72 KB)  

    We have demonstrated state-of-the-art performance of AlGaN/GaN heterojunction bipolar transistors (HBTs) with a common emitter (CE) current gain of 31 at 175 K and 11.3 at 295 K. The increase in collector current and CE current gain at lower temperature can be attributed to the reduced base-emitter interface recombination current. We also observed an increase of collector-emitter offset voltage with decrease of temperature. The increase of V/sub CEOFF/ at lower temperature is related to an increase of V/sub BE/ as the base bulk current is increased, or to the reduction of the ideality factor n/sub BE/. View full abstract»

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  • Low-operation voltage of InGaN/GaN light-emitting diodes by using a Mg-doped Al/sub 0.15/Ga/sub 0.85/N/GaN superlattice

    Publication Year: 2001 , Page(s): 160 - 162
    Cited by:  Papers (30)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (57 KB)  

    Low-resistivity Mg-doped Al/sub 0.15/Ga/sub 0.85/N/GaN strained-layer superlattices were grown. In these superlattices, the maximum hole concentration is 3/spl times/10/sup 18//cm/sup 3/ at room temperature. Hall-effect measurements indicate high conductivity of this structure in which the high activation efficiency is attributed to the strain-induced piezoelectric fields. This work also fabricated InGaN/GaN blue LEDs that consist of a Mg-doped Al/sub 0.15/Ga/sub 0.85/N/GaN SLs. Experimental results indicate that the LEDs can achieve a lower operation voltage of around 3 V, i.e., smaller than conventional devices which have an operation voltage of about 3.8 V. View full abstract»

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  • Optimum Au/WSi 0.3 μm-gate-length n-HIGFETs for microwave power applications in X band

    Publication Year: 2001 , Page(s): 163 - 165
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (103 KB)  

    An investigation of pseudomorphic Ga/sub 0.25/Al/sub 0.75/As/Ga/sub 0.80/In/sub 0.20/As/GaAs heterostructure insulated-gate FETs (HIGFET) far microwave power applications is presented. Devices have been fabricated using Au/WSi self-aligned gate technology with SiO2 sidewalls. The fabrication process has been optimized in order to realize 0.3 μm gate-length transistors with reduced short-channel effects and improved rf power performance. dc and rf extracted parameters suggest very attractive capabilities: for N-type HIGFET, a current density of 460 mA/mm and an extrinsic transconductance of 480 mS/mm are obtained. Measurements at 10 GHz using a load-pull power setup have been carried out: 300 mW/mm maximum output power, 14 dB linear gain, and 65% PAE, for low Vds (3 V) value. To our knowledge, these power results are the first reported for 0.3 μm-HIGFFTs. View full abstract»

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  • A novel in-situ SOI characterization technique: the intrinsic point-probe MOSFET

    Publication Year: 2001 , Page(s): 166 - 169
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (97 KB)  

    This letter presents a novel, simple yet powerful method, called the intrinsic point-probe MOSFET technique, dedicated to accurate in situ evaluation of SOI material electrical parameters. The proposed method is free of parasitic series resistances and is particularly adapted for both static and dynamic investigations. It is essentially based on the inspection of the intrinsic conductance of the inversion channel induced by the substrate bias acting as a gate. Analytical models of the intrinsic conductance and related parameter extraction procedures are presented and validated on state-of-the-art Unibond wafers. View full abstract»

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  • RIE gate-recessed (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs double doped-channel FETs using CHF3+BCl3 mixing plasma

    Publication Year: 2001 , Page(s): 170 - 172
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (74 KB)  

    BCl/sub 3/+CHF/sub 3/ gas mixtures for the reactive ion etching process were applied to the gate-recess for fabricating (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P quaternary heterostructure double doped-channel FET's (D-DCFET), where a high uniformity of Vth was achieved. With the merits of this wide bandgap (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer, microwave power performance of this heterostructure D-DCFET demonstrates a compatible performance for devices fabricated on AlGaAs/InGaAs heterostructures. View full abstract»

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  • A formation of cobalt silicide on silicon field emitter arrays by electrical stress

    Publication Year: 2001 , Page(s): 173 - 175
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (52 KB)  

    A novel process utilizing electrical stress is proposed for the formation of Co silicide on single crystal silicon (c-Si) FEAs to improve the field emission characteristics. Co silicide FEAs formed by electrical stress (ES) exhibited a significant improvement in turn-on voltage and emission current compared with c-Si FEAs. The improvement mainly comes from the lower effective work function of Co silicide and less blunting of tips during silicidation by electrical stress in an ultra high vacuum (UHV) environment less than 10/sup -8/ torr. View full abstract»

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  • Improved inversion channel mobility for 4H-SiC MOSFETs following high temperature anneals in nitric oxide

    Publication Year: 2001 , Page(s): 176 - 178
    Cited by:  Papers (123)  |  Patents (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (52 KB)  

    Results presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO/sub 2/ interface states near the conduction band edge by high temperature anneals in nitric oxide. Hi-lo capacitance-voltage (C-V) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2/spl times/10/sup 13/ to 2/spl times/10/sup 12/ eV/sup -1/ cm/sup -2/ following anneals in nitric oxide at 1175/spl deg/C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 30-35 cm/sup 2//V-s following the passivation anneals. View full abstract»

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  • Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension

    Publication Year: 2001 , Page(s): 179 - 181
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (68 KB)  

    A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from low on-off current ratio, the new device exhibits high on/off current ratio up to 10/sup 6/ for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS process integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications. View full abstract»

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  • High performance Si/Si/sub 1-x/Gex resonant tunneling diodes

    Publication Year: 2001 , Page(s): 182 - 184
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (80 KB)  

    Resonant tunneling diodes (RTDs) with strained i-Si/sub 0.4/Ge/sub 0.6/ potential barriers and a strained i-Si quantum well, all on a relaxed Si/sub 0.8/Ge/sub 0.2/ virtual substrate were successfully grown by ultra high vacuum compatible chemical vapor deposition and fabricated using standard Si processing methods. A large peak to valley current ratio of 2.9 and a peak current density of 4.3 kA/cm/sup 2/ at room temperature were recorded from pulsed and continuous dc current-voltage measurements, the highest reported values to date for Si/Si/sub 1-x/Ge/sub x/ RTDs. These dc figures of merit and material system render such structures suitable and highly compatible with present high speed and low power Si/Si/sub 1-x/Ge/sub x/ heterojunction field effect transistor based integrated circuits. View full abstract»

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  • A novel SCR ESD protection for triple well CMOS technologies

    Publication Year: 2001 , Page(s): 185 - 187
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (37 KB)  

    A novel SCR structure for on-chip ESD protection implemented with a deep submicron triple well CMOS technology is presented. The triple well technology offers the possibility of biasing the p-well, on which the structure is built, under transient ESD stress conditions and independently from the substrate. This greatly affects the turn on mechanism of the structure. Unlike conventional SCR devices, the proposed p-well coupled SCR offers a reduced triggering voltage level as well as the enhanced ESD performance of the SCR devices. The turn on of this structure is realized with a common RC trigger network. The concept is supported by device simulation results. View full abstract»

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  • Separation of hot-carrier-induced interface trap creation and oxide charge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

    Publication Year: 2001 , Page(s): 188 - 190
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (57 KB)  

    By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V/sub gs/ stress, HEIP is found to dominate the shift of threshold voltage V/sub t/. When V/sub gs/ increases to a moderate value, the V/sub t/ shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V/sub gs/ is increased further to V/sub gs/=V/sub ds/. For the first time, the effects of interface trap creation and oxide charge trapping on the V/sub t/ shift are quantified by the proposed technique. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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