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Proceedings of the IEEE

Issue 3 • Date March 2001

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Displaying Results 1 - 12 of 12
  • Special issue on limits of semiconductor technology

    Publication Year: 2001 , Page(s): 223 - 226
    Cited by:  Papers (9)
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    Freely Available from IEEE
  • Scanning our past from London: The filament lamp and new materials

    Publication Year: 2001 , Page(s): 413 - 415
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    A 19th century electrical artifact that has been completely transformed and given a new lease of life is the filament lamp. In the 19th century, the filament was made of carbon: no other material was satisfactory. The author looks at the development of early carbon lamps and the eventual transition to metal filament lamps using tantalum and tungsten. View full abstract»

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  • Fundamental limits of silicon technology

    Publication Year: 2001 , Page(s): 227 - 239
    Cited by:  Papers (41)
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    Measures of the performance of digital electronics have increased steadily for four decades. The essential ingredient of progress has been miniaturization. The road to advances beyond a decade into the future has always been obscure and has stimulated much speculation as to where miniaturization must end. Thus far, new ideas have regularly met the challenges posed by new problems and have allowed the trends to continue. The persistence of silicon as the basis of information technology is the one constant. The problems and solutions arising from changing physics caused by miniaturization are examined in the perspective of the environment in which millions of closely packed devices must function and the external world that information processing technology serves. The complex structure of devices offers considerable room for ingenuity and novel approaches. The large number of devices collected on a single chip of silicon must communicate with one another via a complex array of wires. Miniaturization of the wires poses a different set of questions. The simple structure of a wire offers less scope for invention than is possible with devices and it is more difficult to see solutions to problems. Nevertheless, as has happened in the past, it is difficult to find obviously insuperable barriers to progress in fundamental physics View full abstract»

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  • Interconnect limits on gigascale integration (GSI) in the 21st century

    Publication Year: 2001 , Page(s): 305 - 324
    Cited by:  Papers (192)  |  Patents (59)
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    Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node View full abstract»

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  • Coming challenges in microarchitecture and architecture

    Publication Year: 2001 , Page(s): 325 - 340
    Cited by:  Papers (40)  |  Patents (1)
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    In the past several decades, the world of computers and especially that of microprocessors has witnessed phenomenal advances. Computers have exhibited ever-increasing performance and decreasing costs, making them more affordable and in turn, accelerating additional software and hardware development that fueled this process even more. The technology that enabled this exponential growth is a combination of advancements in process technology, microarchitecture, architecture, and design and development tools. While the pace of this progress has been quite impressive over the last two decades, it has become harder and harder to keep up this pace. New process technology requires more expensive megafabs and new performance levels require larger die, higher power consumption, and enormous design and validation effort. Furthermore, as CMOS technology continues to advance, microprocessor design is exposed to a new set of challenges. In the near future, microarchitecture has to consider and explicitly manage the limits of semiconductor technology, such as wire delays, power dissipation, and soft errors. In this paper we describe the role of microarchitecture in the computer world present the challenges ahead of us, and highlight areas where microarchitecture can help address these challenges View full abstract»

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  • New paradigm of silicon technology

    Publication Year: 2001 , Page(s): 394 - 412
    Cited by:  Papers (5)  |  Patents (8)
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    We present a new paradigm of Si technologies to establish a gigahertz-operation gigascale integrated system large-scale integration (LSI), including digital and analog circuits. According to the theoretical analysis of high-speed signal propagation properties in the practical LSI structure, a gas-isolated-interconnect high-k gate dielectric metal-gate metal-substrate silicon-on-insulator (SOI) LSI structure is proposed as a possible solution for a future gigahertz GSI system LSI, where the clock rate is improved up to beyond 10 GHz and the minimum feature size is reduced down to 0.035 μm in keeping with the continuous progress of the LSI's speed performance. Perfect scientific manufacturing free from fluctuations consisting of total low-temperature high-quality and high-speed processes based on very high-density plasma having very low electron temperatures is essential to realize them View full abstract»

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  • Limitations and challenges of computer-aided design technology for CMOS VLSI

    Publication Year: 2001 , Page(s): 341 - 365
    Cited by:  Papers (16)  |  Patents (5)
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    As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semi-automated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation View full abstract»

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  • Device scaling limits of Si MOSFETs and their application dependencies

    Publication Year: 2001 , Page(s): 259 - 288
    Cited by:  Papers (328)  |  Patents (6)
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    This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications View full abstract»

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  • Limits of lithography

    Publication Year: 2001 , Page(s): 366 - 374
    Cited by:  Papers (29)
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    Lithography technology has been one of the key enablers and drivers for the semiconductor industry for the past several decades. Improvements in lithography are responsible for roughly half of the improvement in cost per function in integrated circuit (IC) technology. The underlying reason for the driving force in semiconductor technology has been the ability to keep the cost for printing a silicon wafer roughly constant while dramatically increasing the number of transistors that can be printed per chip. ICs have always been printed optically with improvements in lens and imaging material technology along with decreases in wavelength used fueling the steady improvement of lithography technology. The end of optical lithography technology has been predicted by many and for many years. Many technologies have been proposed and developed to improve on the performance of optical lithography, but so far none has succeeded. This has been true largely because it has always been more economical to push incremental improvements in the existing optical technology rather than displace it with a new one. At some point in time, the costs for pushing optical lithography technology beyond previously conceived limits may exceed the cost of introducing new technologies. In this paper the author examines the limits of lithography and possible future technologies from both a technical and economic point of view View full abstract»

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  • Analog at milepost 2000: a personal perspective

    Publication Year: 2001 , Page(s): 289 - 304
    Cited by:  Patents (1)
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    Electronics has barely just begun to exploit the endless opportunities for analog techniques. Rather than rendering them obsolete, the recent explosion in digital communications systems has only increased the demand for both fully analog and mixed-signal integrated-circuit (IC) products. This paper is an unashamedly personal and bipolar-centric review of a few selected aspects of the contemporary landscape and offers several reasons for expecting an unending dependence on analog techniques View full abstract»

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  • Material and process limits in silicon VLSI technology

    Publication Year: 2001 , Page(s): 240 - 258
    Cited by:  Papers (41)  |  Patents (2)
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    The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely believed that this process will continue for at least another ten years. However there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur, and beyond ten years there is great uncertainty about the ability to continue scaling metal-oxide-semiconductor field-effect transistor (MOSFET) structures. This paper describes some of the the most challenging materials and process issues to be faced in the future and where possible solutions are known, describes these potential solutions. The paper is written with the underlying assumption that the basic metal-oxide-semiconductor (MOS) transistor will remain the dominant switching device used in ICs and it further assumes that silicon will remain the dominant substrate material View full abstract»

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  • Limits of integrated-circuit manufacturing

    Publication Year: 2001 , Page(s): 375 - 393
    Cited by:  Papers (8)
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    A methodology is suggested for the study of integrated-circuit manufacturing limits. It is based on a hierarchical view of manufacturing detractors and associates limits with levels in this hierarchy. The methodology is illustrated with examples of steady-state, theoretical, and process limits at today's state of the art as well as example projections to future manufacturing at what may be near the limits of complementary metal-oxide-semiconductor (CMOS) scaling. There are also some speculations on possibilities beyond these limits View full abstract»

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H. Joel Trussell
North Carolina State University