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IEE Proceedings - Computers and Digital Techniques

Issue 1 • Date Jan 2001

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Displaying Results 1 - 7 of 7
  • Dynamic synchronous bandwidth allocation scheme for hard real-time communication in FDDI networks

    Publication Year: 2001, Page(s):15 - 22
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (408 KB)

    In a distributed system for hard real-time applications, communication by message exchange between tasks residing on different nodes must happen in bounded time. Due to its timed token MAC protocol, FDDI provides a suitable network structure for these systems. The paper proposes a synchronous bandwidth allocation (SBA) scheme for deadline guarantees of synchronous messages with arbitrary deadlines... View full abstract»

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  • Optimisation in behavioural synthesis using hierarchical expansion: module ripping

    Publication Year: 2001, Page(s):31 - 43
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (996 KB)

    During behavioural synthesis, an abstract functional description of a system is mapped automatically onto a physical structure. In a competitive setting, this mapping is highly optimised (the data flow is re-arranged, units and registers are multiplexed and so on) to deliver a final structure that meets some overall user-supplied specification. Ultimately, however, the physical functional units ar... View full abstract»

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  • Weaknesses of protocols for updating the parameters of an established threshold scheme

    Publication Year: 2001, Page(s):45 - 48
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (348 KB)

    Threshold schemes are adaptable cryptographic primitives that distribute trust in secret data by requiring k out of n entities to co-operate before the data can be recovered. An important security management issue relating to threshold schemes is the problem of updating the parameters of a threshold scheme. The paper discusses serious shortcomings in two proposed protocols for threshold parameter ... View full abstract»

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  • Efficient coverage analysis metric for HDL design validation

    Publication Year: 2001, Page(s):1 - 6
    Cited by:  Papers (2)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (580 KB)

    Simulation is still the primary approach for the functional verification of register-transfer level circuit descriptions written in hardware description language (HDL). The major problem of the simulation approach is to choose a good metric to gauge the quality of the test patterns. The finite state machine (FSM) coverage test can find most of the design errors in a FSM. However, it is impractical... View full abstract»

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  • Finite state machine encoding for VHDL synthesis

    Publication Year: 2001, Page(s):23 - 30
    Cited by:  Papers (13)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (680 KB)

    Finite state machine (FSM) optimisation has usually been studied through state assignment, state vector encoding, and combinational logic optimisation. Such details should not be consequential in behavioural descriptions. On the other hand, describing correct and efficient hardware structures in VHDL (VHSIC hardware description language), or generally in any high-level description language, is mor... View full abstract»

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  • Efficient RNS-to-binary conversion using high-radix SRT division

    Publication Year: 2001, Page(s):49 - 52
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (304 KB)

    A new Chinese remainder theorem (CRT)-based technique for the conversion of numbers in residue number system (RNS) format to binary representation is proposed that employs a high-radix SRT division-like architecture. The major benefit of the new technique is that it permits the efficient conversion of residue numbers with many moduli. A k-modulus RNS converter returning a w-bit result employs a([l... View full abstract»

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  • PLI logic for multiple-valued functions

    Publication Year: 2001, Page(s):7 - 14
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (648 KB)

    Properties of transformation matrices for multiple-valued-input binary-output PLI logic are discussed. It is shown that some of PLI logic transformations for Boolean functions are still applicable for multiple-valued-input binary functions with appropriate coding and new matrix functions. Fast algorithms of suitable PLI transformation matrices are shown and their complexity analysis is discussed View full abstract»

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