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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 1 • Date Jan 2001

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Displaying Results 1 - 17 of 17
  • A programmable continuous-time floating-gate Fourier processor

    Page(s): 90 - 99
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    We present a programmable continuous-time floating-gate Fourier processor that decomposes the incoming signal into frequency bands by analog bandpass filters, multiplies each channel by a nonvolatile weight, and then recombines the frequency channels. A digital signal processor would take a similar approach of computing a fast Fourier transform (FFT), multiplying the frequency components by a weight and then computing an inverse PFT. We decompose the frequency bands of the incoming signal using the transistor-only version of the autozeroing floating-gate amplifier (AFGA), also termed the capacitively coupled current conveyer (C4). Each band decomposition is then fed through a floating-gate multiplier to perform the band weighting. Finally, the multiplier outputs are summed using Kirchoff current law to give a band-weighted output of the original signal. We examine many options to reduce second-order harmonic problems inherent in the single-sided C4. We present a method for programming arrays of floating-gate devices that are used in the weighting of the bands. All of these pieces fit together to form an elegant and systematic Fourier processor View full abstract»

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  • Low-voltage CMOS op-amp with rail-to-rail input and output signal swing for continuous-time signal processing using multiple-input floating-gate transistors

    Page(s): 111 - 116
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    A scheme for low-voltage CMOS op-amp operation with rail-to-rail input and output signal swing and constant gm is presented. Single-ended and fully differential versions are discussed. The scheme is based on the use of multiple-input floating-gate transistors and allows direct implementation of linear weighted addition of continuous-time signals. Simulations are presented that verify the scheme operating with a 1.2-V single supply, 1.2-V input and output solving, 5-MHz op-amp gain-bandwidth product, and a 192-μW power dissipation with a 50-pF load and 300×300 μm2 silicon area. These results are obtained for 0.85-V transistor threshold voltages. Experimental results are shown that verify the correct functionality of the proposed approach View full abstract»

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  • Continuous-time feedback in floating-gate MOS circuits

    Page(s): 56 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    We present the negative- and positive-feedback circuit configurations of continuous-time floating-gate MOS circuits. We start by reviewing the dynamics of our pFET and nFET single-transistor synapses. We present the range of possible stabilizing and destabilizing types of feedback in circuits with one floating-gate synapse, including data from nFET and pFET synapses. We then show examples of competitive and cooperative behavior in multiple-synapse circuits. We present experimental data from circuits fabricated in the 2-μm n-well CMOS process available through MOSIS. We see similar experimental effects in 1.2and 0.5-μm processes View full abstract»

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  • A programmable current mirror for analog trimming using single poly floating-gate devices in standard CMOS technology

    Page(s): 100 - 102
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (108 KB) |  | HTML iconHTML  

    This paper describes a programmable current mirror comprised of single-poly floating-gate devices. By programming the threshold voltage of the floating-gate devices, a current mirror's input-output current mismatch can be trimmed at a desired current level. This programmability allows accurate drain current matching to be achieved without using large gate area devices. A prototype of the programmable current mirror fabricated in a 0.5-micron digital CMOS technology achieves 0.04% input-output current matching View full abstract»

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  • Ultra-low-voltage floating-gate transconductance amplifiers

    Page(s): 37 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB) |  | HTML iconHTML  

    Ultra-low-voltage (ULV) floating-gate differential amplifiers are presented. In this paper, we present several different approaches to CMOS ULV amplifier design. Sinh-shaped and tanh-shaped transconductance amplifiers are described. Measured results are provided View full abstract»

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  • A CMOS programmable analog memory-cell array using floating-gate circuits

    Page(s): 4 - 11
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this paper, we present a design for an on-chip nonvolatile analog memory cell that can be configured in addressable arrays and programmed easily. We use floating-gate MOS transistors to store charge, and we use the processes of tunneling and hot-electron injection to program values. We have fabricated two versions of this design: one with an nFET injection mechanism and one with a pFET injection mechanism. With these designs, we achieve greater than 13-bit output precision with a 39-dB power-supply rejection ratio and no crosstalk between memory cells View full abstract»

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  • A second-order section built from autozeroing floating-gate amplifiers

    Page(s): 116 - 120
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    We introduce the autozeroing floating-gate (AFGA) second-order section. We built this second-order filter where the corner frequency and Q are electronically tunable based on a classic filter topology and principles of operational transconductance amplifiers. We built this second-order filter using three AFGAs-our floating-gate amplifier that sets its operating point by the interaction of hot-electron injection and electron tunneling View full abstract»

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  • An autozeroing floating-gate amplifier

    Page(s): 74 - 82
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    We have developed a bandpass floating-gate amplifier that uses tunneling and pFET hot-electron injection to set its dc operating point adaptively. Because the hot-electron injection is an inherent part of the pFET's behavior, we obtain this adaptation with no additional circuitry. Because the gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high-frequency cutoff is controlled electronically, as is done in continuous-time filters. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data for a wide range of operating conditions and input waveforms. This autozeroing floating-gate amplifier demonstrates how to use continuous-time floating-gate adaptation in amplifier design View full abstract»

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  • Correlation learning rule in floating-gate pFET synapses

    Page(s): 65 - 73
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB) |  | HTML iconHTML  

    We study the weight dynamics of the floating-gate pFET synapse and the effects of the pFET's gate and drain voltages on these dynamics. We show that we can derive a weight update rule such that the equilibrium weight value is proportional to the correlation between the gate and drain voltages. In particular, we want a rule of the form τ' ΔW˙=-ΔW+ηE[xy], where x is a voltage signal on the gate terminal and y is a voltage signal on the drain terminal. We obtain this rule by making a linear approximation to the weight dynamics around a given equilibrium point. We develop this approximation by considering the basic functional form of the system dynamics and then examining the effects of the gate and drain voltages on the specifics of this form View full abstract»

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  • Floating-gate adaptation for focal-plane online nonuniformity correction

    Page(s): 83 - 89
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    Stochastic adaptive algorithms are investigated for online correction of spatial nonuniformity in random-access addressable imaging systems. The adaptive architecture is implemented in analog VLSI, integrated with the photosensors on the focal plane. Random sequences of address locations selected with controlled statistics are used to adaptively equalize the intensity distribution at variable spatial scales. Through a logarithm transformation of system variables, adaptive gain correction is achieved through offset correction in the log-domain. This idea is particularly attractive for compact implementation using translinear floating-gate MOS circuits. Furthermore, the same architecture and random addressing provide for oversampled binary encoding of the image with equalized intensity histogram. The techniques apply to a variety of solid-state imagers, such as artificial retinas, active pixel sensors, and IR sensor arrays. Experimental results confirm gain correction and histogram equalization in a 64×64 pixel adaptive array integrated on a 2.2-mm×2.25-mm chip in 1.2-μm CMOS technology View full abstract»

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  • Floating-gate-based tunable CMOS low-voltage linear transconductor and its application to HF gm-C filter design

    Page(s): 106 - 110
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    This paper presents a new CMOS low-voltage linear transconductor for very high frequency. It uses multiple-input floating-gate transistors in each inverter of the differential structure transconductor presented by Nauta [1992]. The proposed transconductor operates under a constant low-voltage supply as low as 1.2 V, and its transconductance and output resistance are independently tunable, as shown by experimental measurements. This architecture is suitable for use in high-frequency continuous-time filters with programmable center frequency and quality factor. Simulation results of a 10.7-MHz and Q=40 gm-C filter operating with a voltage supply of 1.4 V and with rail-to rail input swing are presented View full abstract»

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  • A practical floating-gate Muller-C element using vMOS threshold gates

    Page(s): 102 - 106
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation View full abstract»

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  • MITE circuits: the continuous-time counterpart to switched-capacitor circuits

    Page(s): 45 - 55
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB) |  | HTML iconHTML  

    Some new applications of a family of circuits using op-amps built with multiple-input translinear elements (MITE) circuits are discussed. These include weighted average circuits for resistive networks, defuzzifiers, FIRs, common-mode feedback networks, sigma-delta modulators, and fast digital converters (digital-analog and analog-digital). Some aspects of MITE circuits not reported before are discussed like gain-bandwidth tradeoffs and an analysis showing that the behavior of closed-loop MITE circuits is determined by accurately controllable capacitance ratios; to a first-order approximation it is not affected by the parasitic capacitances of the MOS transistor. From this point of view MITE circuits are considered here as the continuous-time counterpart to switched-capacitor circuits. Experimental results of two test chip prototypes are shown View full abstract»

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  • Multiple-input translinear element log-domain filters

    Page(s): 29 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    Describes the implementation of log-domain filters with multiple-input translinear elements (MITEs). Such circuit elements produce output currents that are exponential in a weighted sum of their input voltages. The author discusses the operation of the MITE building block circuit from which he constructs MITE log-domain filters. Then, he analyzes the behavior of a first-order low-pass MITE log-domain fitter, the simplest such circuit. He also presents a fully tunable second-order low-pass MITE log-domain filter with experimental measurements of a version of the second-order filter that was fabricated in a 1.2-μm double-poly CMOS process with an npn bipolar option. The author also describes a simple procedure for synthesizing MITE log-domain filters from state-space descriptions. He can obtain such state-space descriptions from a variety of sources; the procedure described can be used regardless of the source of the description. We can often derive such descriptions conveniently from already extant filters that have been previously implemented within a different class of filters. The synthesis procedure is illustrated by deriving two simple MITE log-domain filters from single-ended voltage-mode operational transconductance amplifier C filter prototypes View full abstract»

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  • Multiple-input translinear element networks

    Page(s): 20 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB) |  | HTML iconHTML  

    We describe a new class of translinear circuits that accurately embody product-of-power-law relationships in the current signal domain. We call such circuits multiple-input translinear element (MITE) networks. A MITE is a circuit element, which we defined recently that produces an output current that is exponential in a weighted sum of its input voltages. We describe intuitively the basic operation of MITE networks and provide a systematic matrix technique for analyzing the nonlinear relationships implemented by any given circuit. We also show experimental data from three MITE networks that were fabricated in a 1.2-μm double-poly CMOS process View full abstract»

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  • Programming floating-gate circuits with UV-activated conductances

    Page(s): 12 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB) |  | HTML iconHTML  

    A programming technique for controlling the floating gates (FGs) in ultra-low-voltage (ULV) floating-gate circuits is presented. Simple ULV PG current-scaling and level-shifting circuits are discussed. The current scaling and level shifting are accomplished using only minimum sized transistors and floating capacitors. Floating-gate current multiplier and divider circuits are described. Measured results are provided, View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope