By Topic

Solid-State Circuits, IEEE Journal of

Issue 3 • Date March 2001

Filter Results

Displaying Results 1 - 25 of 31
  • Editorial

    Page(s): 312 - 314
    Save to Project icon | Request Permissions | PDF file iconPDF (29 KB)  
    Freely Available from IEEE
  • A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet

    Page(s): 374 - 384
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (223 KB)  

    1000BASE-T Gigabit Ethernet employs eight-state 4-dimensional trellis-coded modulation to achieve robust 1-Gb/s transmission over four pairs of Category-5 copper cabling. This paper compares several postcursor equalization and trellis decoding algorithms with respect to performance, hardware complexity, and critical path. It is shown that parallel decision-feedback decoders (PDFD) offer the best tradeoff. The example of a 14-tap PDFD, however, shows that it is challenging to meet the required throughput of 1 Gb/s using current standard-cell CMOS technology. A modified approach is proposed which uses decision-feedback prefilters followed by a one-tap PDFD. This considerably reduces hardware complexity and improves the throughput while still meeting the bit-error-rate requirement. The critical path is further reduced by employing a look-ahead technique. The proposed joint equalizer and trellis decoder architecture has been implemented in 3.3-V 0.25-μm standard-cell CMOS process. It achieves a throughput of 1 Gb/s with a 125 MHz clock. Compared to a 14-tap PDFD, the design improves both gate count and throughput by a factor of two, while suffering only from a 1.3-dB performance degradation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

    Page(s): 432 - 439
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 27-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm2 View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops

    Page(s): 385 - 397
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB) |  | HTML iconHTML  

    The recycling integrator correlator (RIC) is a novel approach for implementing correlators that consumes less power than conventional digital or analog CMOS correlators. The RIC modulates the product of a received signal and a pseudorandom noise (PN) sequence into a bit stream by first-order ΔΣ modulation. The accumulated number represents the quantized correlation value. Using RICs, two functional blocks of a direct sequence code division multiple access (DS-CDMA) demodulator targeting IMT-2000, a matched filter (MF) and a delay locked-loop (DLL) are implemented in silicon. In the fabricated 256-tap QPSK MF-RIC, two 256-tap double-sampling MFs sample the I and Q received analog signals at a rate of 8 Msample/s. Their outputs are 9-bit quantized correlation values with a 256-chip PN sequence at the same rate as the sampling rate. The DLL-RIC can adapt to spreading ratios from 32 to 256 with the use of an auxiliary ADC that can compensate the degradation of dynamic range when the spreading ratio is small. Processed in a 0.35-μm CMOS process, the MF-RIC and the DLL-RIC, respectively, occupy 22.8 and 2.28 mm2 and dissipate 23.0 and 3.4 mW at 2-V power supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire

    Page(s): 366 - 373
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    A discrete-time analog echo canceller is described that reduces the echo in the front end of Gigabit Ethernet twisted-pair interfaces. Echo cancellation in the analog domain by means of four taps reduces the complexity of the digital echo canceller and crosstalk cancellers. Designed in a 0.4-μm CMOS technology, the circuit employs an LMS algorithm to adapt to the cable length and impedance discontinuities, providing an echo suppression of 10 dB. The design operates at 125 MHz while consuming 43 mW from a 3-V supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A frequency-agile single-chip QAM modulator with beamforming diversity

    Page(s): 398 - 407
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    Architecture and circuit design techniques for VLSI implementation of a single-chip quadrature amplitude modulation (QAM) modulator with frequency agility and antenna beamforming characteristics are presented. In order to achieve reliable wireless communication modem function, the single chip all-digital QAM modulator implements various features, including high data rates with bandwidth efficiency, flexibility, meeting a wide variety of user throughput requirements with variable and width and data rates in a multi-user system, and robustness, incorporating diversity and redundancy techniques to guarantee robust communication for various operating environments. The modulator components consist of several digital processing building blocks, including various finite-impulse-response (FIR) filters, an innovative variable interpolation filter, a four-channel frequency translator with quadrature mixer for antenna beamforming diversity, a quadrature direct digital frequency synthesizer (QDDFS), a numerically controlled oscillator (NCO), a QAM formatter, a pseudorandom noise (PN) generator, an x/sinx filter, and a microcontroller interface. An optimized architecture and chip implementation for the variable modulator is derived and evaluated which will support symbol rates from 6 kBaud to 8.75 MBaud continuously and digitally flexible IF frequencies up to 70 MHz with four-channel antenna beamforming function View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme

    Page(s): 566 - 569
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (64 KB) |  | HTML iconHTML  

    A 20-bit delta-sigma A/D converter is implemented in a 0.6-μm CMOS process with a single 5-V supply. It provides a 25-kHz data rate for high-speed dc measurement while maintaining good the performance required for accurate dc measurement such as noise, linearity and drift. The front-end programmable gain amplifier (PGA) allows the user to optimize their system for different input ranges. Offset and finite gain compensation are used in the PGA section to reduce offset and improve linearity performance of the amplifier. In the delta-sigma converter section, low frequency error reduction is achieved through the use of chopper stabilization technique. A frequency-shaped chopper stabilization scheme is used to alleviate the intermodulation tone problem commonly associated with the use of the fixed rate chopping in delta-sigma modulators. This A/D converter achieves 2.5 ppm RMS noise and 12 ppm INL at gain of one View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Direct digital frequency synthesis of low-jitter clocks

    Page(s): 570 - 572
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    This paper presents a new phase correction technique applicable to phase accumulators that allows them to express arbitrary rational divide ratios such as R=N/M. Compared to existing methods, the technique gives better results in terms of jitter, and it simplifies design and implementation of practical direct digital synthesis circuits. A typical application of the proposed technique is digital television, where combinations of existing standards lead to the need to synchronize exactly a 6.144-MHz audio clock with a 35.46895-MHz video clock. This implies a divide ratio of R=122880/709379 View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver

    Page(s): 452 - 466
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility. Their design highlights the tradeoff between performance, lifetime, cost, and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation). These considerations are illustrated by the design of a prototype receiver chip realized in a standard 0.5-μm digital CMOS process with 0.6-V threshold voltage. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit operates at 1-V power supply in the 434-MHz European ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kb/s View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

    Page(s): 522 - 527
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB) |  | HTML iconHTML  

    This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A Vdd/2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

    Page(s): 315 - 324
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than ±0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-μm CMOS technology and has an active area of only 0.35 mm2 View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V

    Page(s): 331 - 338
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB) |  | HTML iconHTML  

    A 100-MS/s 8-b CMOS analog-to-digital converter (ADC) designed for very low supply voltage and power dissipation is presented. This single-ended-input ADC is based on the unified two-step subranging architecture, which processes the coarse and fine decisions in identical signal paths to maximize their matching. However, to minimize power and area, the coarse-to-fine overlap correction has been aggressively reduced to only one LSB. The ADC incorporates five established design techniques to maximize performance: bottom-plate sampling, distributed sampling, autozeroing, interpolation, and interleaving. Very low voltage operation required for a general purpose ADC was obtained with four additional and new circuit techniques. These are a dual-gain first-stage amplifier, differential T-gate boosting, a supply independent delay generator, and a digital delay-locked-loop controlled output driver. For a clock rate of 100 MS/s, 7.0 (7.3) effective bits for a 50 MHz (10 MHz) input are maintained from 3.8 V down to 2.2 V. At 2.2 V, this 100-MS/s converter dissipates 75 mW plus 9 mW for the reference ladder. For a typical supply of 2.7 V, it consumes just 1 mW per MS/s over the 10-160-MS/s clock frequency range. Differential nonlinearity below 0.5 LSB is maintained from 2.7 V down to 2.2 V, and it degrades only slightly to 0.8 LSB at 3.8-V supply. The converter is implemented in a 0.35-μm CMOS process, with double-poly capacitors and no low-threshold devices View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

    Page(s): 417 - 423
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB) |  | HTML iconHTML  

    This paper describes a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator. Both of these circuits employ a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up; it can recover from missing reference clock pulses and, because the delay range is not restricted, it can accommodate a variable reference clock frequency. The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer, and provides temperature-compensated biasing for the tunable oscillator. With a 2-V supply the measured rms jitter for the 1-GHz synthesizer output was 3.2 ps. With a 3.3-V supply, rms jitter of 3.1 ps was measured for a 1.6-GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0°C to 85°C. The circuits were fabricated on a generic 0.5-μm digital CMOS process View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 0.5-μm CMOS T/R switch for 900-MHz wireless applications

    Page(s): 486 - 492
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    A single-pole double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-μm CMOS process. An analysis shows that substrate resistances and source/drain-to-body capacitances must be lowered to decrease insertion loss. The switch exhibits a 0.7-dB insertion loss, a 17-dBm power 1-dB compression point (P1 dB), and a 42-dB isolation at 928 MHz. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the power 1-dB compression point. The switch has adequate insertion loss, isolation, P1 dB, and IP3 for a number of 900-MHz ISM band applications requiring a moderate peak transmitter power level (~15 dBm) View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dynamic current mode logic (DyCML): a new low-power high-performance logic style

    Page(s): 550 - 558
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB) |  | HTML iconHTML  

    This paper introduces a new reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. Unlike CML circuits, DyCML gates do not have a static current source, which makes DyCML a good candidate for portable devices and battery-powered systems. Simulation and test results show that DyCML circuits are superior to other logic styles in terms of power and delay. A 16-bit DyCML carry look-ahead adder (CLA), fabricated in 0.6-μm CMOS technology, attains a delay of 1.24 ns and dissipates 19.2 mW at 400 MHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 64-min single-chip voice recorder/player using embedded 4-b/cell flash memory

    Page(s): 516 - 521
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB) |  | HTML iconHTML  

    A system-on-chip prototype implementing a full integration of a 64-minute digital voice recorder/player and embedding a 4-b/cell multilevel digital flash memory is presented in this paper. A hardwired adaptive-differential pulse-code modulation speech coder/decoder (8 to 40 kb/s) and a microcontroller are integrated into a bus-centric architecture. An 8-Mcell/32-Mb multilevel flash memory is used as an embedded mass storage media and a fully digital on-chip built-in-self-test solution is presented. This speech recording system features a modular architecture allowing full reuse and mix-and-match of its IP building blocks. The architecture of the system and solutions for implementing embedded multilevel flash memories are presented. System operation modes are described showing how the desired message editing functionality is implemented by a mixed hardware/software solution. The chip is 3-V-only and it counts 13 M transistors at 225 mm2 area in a 0.5-μm embedded flash technology View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%

    Page(s): 503 - 509
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the high-speed circuit design, a multiword redundancy scheme and Y-select merged sense scheme are developed to achieve the performance goal. In the low-voltage design, a dual-complement charge-pump scheme and a decoupling capacitor utilizing a tantalum-oxide capacitor are developed to retain high performance at low supply voltage View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An ultralow-power UHF transceiver integrated in a standard digital CMOS process: transmitter

    Page(s): 467 - 472
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    In the first part of the paper, also in this issue of the JOURNAL, the design of the frequency synthesizer and receiver section of an FSK transceiver was described. It operates in the 434-MHz ISM (Industrial, Scientific, Medical) band and is realized in a standard digital 0.5-μm CMOS process. This companion paper focuses on the realization of the transmitter section. It includes a power amplifier, an upconverter, and the circuit generating the baseband quadrature signals with a continuous phase modulation. The overall measured efficiency of the packaged circuit is higher than 38% for a 1.2-V supply and an output power reaching 10 dBm at 433 MHz. The system is designed to still operate at 1-V supply, delivering more than 1 mW with an efficiency higher than 15% View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 5.5-V I/O in a 2.5-V 0.25-μm CMOS technology

    Page(s): 528 - 538
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB) |  | HTML iconHTML  

    A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-μm CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Physical design guides for substrate noise reduction in CMOS digital circuits

    Page(s): 539 - 549
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    Substrate noise injection in large-scale CMOS logic integrated circuits is quantitatively evaluated by 100-μV 100-ps resolution substrate noise measurements of controlled substrate noises by a transition-controllable noise source and practical substrate noises under CMOS logic operations. The noise injection is dominated by leaks of supply/return bounce into the substrate, and the noise intensity is determined by logic transition activity, according to experimental observations. A time-series divided parasitic capacitance model is derived as an efficient estimator of the supply current for simulating the substrate noise injection and can reproduce the measured substrate noise waveforms. The efficacy of physical noise reduction techniques at the layout and circuit levels is quantified and limitations are discussed in conjunction with the noise injection mechanisms. The reduced supply bounce CMOS circuit is proposed as a universal noise reduction technique, and more than 90% noise reduction to conventional CMOS is demonstrated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Secure contactless smartcard ASIC with DPA protection

    Page(s): 559 - 565
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB) |  | HTML iconHTML  

    A secure contactless smartcard is presented. No batteries are required as device power is extracted from the RF field. With the exception of an inductive loop antenna, no external components are required. The transceiver adheres to the ISO 14443 type B specification. This system-on-a-chip integrates the RF circuitry with a large digital circuit without benefit of external bypass capacitors. An isolation circuit is introduced that prevents coupling of digital noise into the receiver. A measured bit error rate of 3E-10 is achieved. Security is also improved as the isolation circuit increases the required time for differential power analysis (DPA) attack by a factor of 222. Three-pass mutual authentication is presented and an algorithm for data restoration in the event of a tear is shown. This device was fabricated in a 0.6-μm double-poly, triple-metal CMOS process. The chip is 2.8 mm×2.9 mm and it requires 500 uA or approximately 2.5 mW of power View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop

    Page(s): 424 - 431
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB) |  | HTML iconHTML  

    A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-μm CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (KVCO) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-power CMOS super-regenerative receiver at 1 GHz

    Page(s): 440 - 451
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    A low-power and low-voltage super-regenerative receiver operating at 1 GHz and implemented in a 0.35-μm CMOS process is described. The receiver includes a low-noise amplifier, a super-regenerative oscillator, an envelope detector, an AGC circuit with sample/hold function, and a baseband amplifier. The die surface is equal to 0.25 mm 2. The power consumption is less than 1.2 mW at VDD=1.5 V. A 100-kHz sawtooth quench signal is used to achieve a rejection of -36 dB at 500 KHz from the central frequency View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-performance flexible all-digital quadrature up and down converter chip

    Page(s): 408 - 416
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB) |  | HTML iconHTML  

    In this paper, the design of an all-digital quadrature up and down converter with high accuracy and flexible intermediate frequency (IF) settings is presented. The signal up or down conversion is achieved by interpolation and decimation combined with a programmable anti-alias filter to preserve the selected frequency band during the sample rate conversion. This way a high-speed solution with low power consumption is obtained. A novel technique, based on the use of canonic signed digit (CSD) code, was utilized to implement the programmable anti-alias filter structure. The resulting chip fabricated in a 0.5-μm CMOS process is capable of handling sample rates up to 160 megasamples per second (MSPS) and is suitable for coaxial access network modem applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A broadband 10-GHz track-and-hold in Si/SiGe HBT technology

    Page(s): 325 - 330
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB) |  | HTML iconHTML  

    High-performance multistage data converters and sub-sampling frequency downconverters typically require track and hold amplifiers (THAs) with high sampling rates and high linearity. This paper presents a THA for sub-sampling communications applications based on a diode bridge design with high-speed Schottky diodes and an improved current source approach for enhanced linearity. Implemented in a 45-GHz BiCMOS Si/SiGe process, this IC has an input bandwidth in excess of 10 GHz, consumes approximately 550 mW, and can accommodate input voltages up to 600 mV. With an input frequency of 8.05 GHz and a sampling frequency of 4 GHz, the THA has an IIP3 of 26 dBm and a spurious free dynamic range of 30 dB View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan