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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb 2001

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Displaying Results 1 - 9 of 9
  • A learning approach of wafer temperature control in a rapid thermal processing system

    Page(s): 1 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB) |  | HTML iconHTML  

    This paper presents a learning approach for wafer temperature control in a rapid thermal processing system (RTP). RTP is very important for semiconductor processing system and requires an accurate trajectory following. Numerous studies have addressed this problem and most research on this problem requires exact knowledge of the system dynamics. The various approaches do not guarantee the desired performance in practical applications when there exist some modeling errors between the model and the actual system. In this paper, iterative learning control scheme is applied to RTP without exact information on the dynamics. The learning gain of the iterative learning law is estimated by neural networks instead of a mathematical model. In addition, the control information obtained by the iterative learning controller (ILC) is accumulated in the feedforward neuro controller (FNC) for generalization to various reference profiles. Through numerical simulations, it is demonstrated that the proposed method can achieve an accurate output tracking even without an exact RTP model. The output errors decrease rapidly through iterations when using the learning gain estimated and the FNC yields a reduced initial error, and so requires small iterations View full abstract»

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  • Scenario analysis of demand in a technology market using leading indicators

    Page(s): 65 - 75
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB) |  | HTML iconHTML  

    This paper proposes an approach to analyzing demand scenarios in technology-driven markets where product demands are volatile, but follow a few identifiable lifecycle patterns. After examining a large amount of semiconductor data, we found that not only can products be clustered by lifecycle patterns, but in each cluster there exists a leading indicator product that provides advanced indication of changes in demand trends. Motivated by this finding, we propose a scenario analysis structure in the context of stochastic programming. Specifically, the demand model that results from this approach provides a mechanism for building a scenario tree for semiconductor demand. Using the Bass growth model and a Bayesian update structure, the approach streamlines scenario analysis by focusing on parametric changes of the demand growth model over time. The Bayesian structure allows expert judgment to be incorporated into scenario generation while the Bass growth model allows an efficient representation of time varying demands. Further, by adjusting a likelihood threshold, the method generates scenario trees of different sizes and accuracy. This structure provides a practical scenario analysis method for manufacturing demand in a technology market. We demonstrate the applicability of this method using real semiconductor data View full abstract»

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  • A decision support system for spare parts management in a wafer fabrication facility

    Page(s): 76 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB)  

    We present a decision support system for spare parts management in a wafer fabrication facility. The system is based on an analytical stochastic inventory model, which calculates the reorder level and quantity for each part to attain a specified service level. Results from our simulation study indicate that the policies suggested by the system either improve the service level or reduce the operating cost View full abstract»

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  • Hazards of dichlorosilane exhaust deposits from the high-temperature oxide process as determined by FT-ICR mass spectrometry

    Page(s): 20 - 25
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB) |  | HTML iconHTML  

    Gas samples from the exhaust system of tools employing dichlorosilane (DCS) in high temperature oxide (HTO) deposition that produced flammable solid deposits have been analyzed by Fourier transform ion cyclotron resonance (FT-ICR) mass spectrometry. Exact mass determinations by the high-resolution FT-ICR allowed the identification of various polysiloxane species present in such an exhaust flow. Ion-molecule reactions of dichlorosilyl cation with water and DCS indicate the preferred reaction pathway is disiloxane formation through HCl loss, a precursor to the highly flammable polysiloxanes that were identified in the gaseous exhaust and in exhaust deposits. Minimization of these hazardous deposits is discussed with respect to water contamination, dilution factor and water scrubbing of the HTO exhaust View full abstract»

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  • Cycle-time improvements for photolithography process in semiconductor manufacturing

    Page(s): 48 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    Cycle-time reduction is of great importance to semiconductor manufacturers. Photolithography, being one of the most repeated processes, is an area where substantial improvements can be made. We investigate the effects of various process control mechanisms for photolithography on the cycle-time at the process and at the overall fab via a simulation study. Test run policy at the photolithography station, test run frequency, duration of inspection, and machine dedication policy for the equipment are the factors we consider. Equipment down time due to preventive or breakdown maintenance and rework rates are also taken into account. Parallel testing, where test wafer is inspected while the lot is being processed, is the best policy in terms of cycle-time performance. Long inspection time and infrequent, long down times have the most adverse effects, but flexible machine assignment may reduce the impact of down times. Test run frequency is only significant for serial testing, where processing of the lot is not finished until the failed test wafer is stripped and reworked View full abstract»

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  • High-resolution transmission electron microscopy calibration of critical dimension (CD) reference materials

    Page(s): 26 - 31
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB) |  | HTML iconHTML  

    The National Institute of Standards and Technology and Sandia National Laboratories have developed a procedure for producing and calibrating critical dimension (CD), or linewidth, reference materials. These reference materials will be used to calibrate metrology instruments used in semiconductor manufacturing. The reference features, with widths down to 100 nm, are produced in monocrystalline silicon with all feature edges aligned to specific crystal planes. A two-part calibration of these linewidths is used: the primary calibration, with accuracy to within a few lattice plane thicknesses, is accomplished by counting the lattice planes across the sample as-imaged through use of high-resolution transmission electron microscopy. The secondary calibration is the high-precision electrical CD technique. In this paper, we describe the calibration procedure for these reference materials and estimate the related uncertainties View full abstract»

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  • Age-based double EWMA controller and its application to CMP processes

    Page(s): 11 - 19
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB) |  | HTML iconHTML  

    In the originally proposed run-by-run control scheme, the EWMA statistic is used as an estimate of the process deviation from its target. However, the controller based on the EWMA statistic is not sufficient for controlling a wearing out process. The PCC controller has been thus proposed to enhance the run-by-run controller capability. In this paper, we first reexamine the fundamentals of the PCC formulations and propose an adjustment that is advantageous in controlling processes subject to both random shifts and drifts. The adjusted PCC controller is then further refined to take into account the process age. This age-based double EWMA scheme is then applied to the CMP process, which is known in the semiconductor industry to be rather unstable View full abstract»

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  • Optimal bidirectional spine layout for overhead material handling systems

    Page(s): 57 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    Overhead automated material handling systems have become the only material handling solution in semiconductor fabs to achieve zero footprint material handling in the expensive cleanroom floor. This paper provides two rectilinear layout configurations, single-spine and double-spine, for overhead track design. Given the locations of loadports and a pod from-to flow matrix, we determine the rectilinear layout of material flow systems with the objective of minimizing the total loaded travel distances. The optimal single-spine problem can be transformed to a known single-facility layout problem and solved with a linear-time algorithm. The optimal double-spine layout is obtained from the optimal single X-spine and Y-spine and is formulated as an allocation problem. We demonstrate the system designs by a numerical example. The resulting spine layouts are then compared with the Minimum Rectilinear Steiner Tree (MRST) and Shortest Rectilinear Flow Network (SRFN) layouts. MRST layout provides the shortest track length while the SRFN layout guarantees the shortest flow distances. The result shows that spine layout is a potential track layout pattern with respect to simplicity, track lengths and flow distances for overhead flow systems View full abstract»

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  • A system model for feedback control and analysis of yield: A multistep process model of effective gate length, poly line width, and IV parameters

    Page(s): 32 - 47
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (756 KB)  

    We present a large system model capable of producing Pareto charts for several yield metrics, including effective channel length, poly line width, Ion and Isub. These Pareto charts enable us to target specific processes for improvement of the yield metric(s). Our neural network model has an accuracy of 80% and can be trained with a small data set to minimize the feedback time in the control loop for the yield. The system we describe has been implemented in a Lucent Technologies microelectronics lab in Orlando, FL View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Anthony Muscat
Department of Chemical and Environmental Engineering
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University of Arizona
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