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Computers, IEEE Transactions on

Issue 2 • Date Feb 2001

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Displaying Results 1 - 8 of 8
  • Optimal reward-based scheduling for periodic real-time tasks

    Publication Year: 2001 , Page(s): 111 - 130
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB) |  | HTML iconHTML  

    Reward-based scheduling refers to the problem in which there is a reward associated with the execution of a task. In our framework, each real-time task comprises a mandatory and an optional part. The mandatory part must complete before the task's deadline, while a nondecreasing reward function is associated with the execution of the optional part, which can be interrupted at any time. Imprecise computation and Increased-Reward-with-Increased-Service models fall within the scope of this-framework. In this paper, we address the reward-based scheduling problem for periodic tasks. An optimal schedule is one where mandatory-parts complete in a timely manner and the weighted average reward is maximized. For linear and concave reward functions, which are most common, we 1) show the existence of an optimal schedule where the optional service time of a task is constant at every instance and 2) show how to efficiently compute this service time. We also prove the optimality of Rate Monotonic Scheduling (with harmonic periods), Earliest Deadline First, and Least Laxity First policies for the case of uniprocessors when used with the optimal service times we computed. Moreover, we extend our result by showing that any policy which can fully utilize all the processors is also optimal for the multiprocessor periodic reward-based scheduling. To show-that our optimal solution is pushing the limits of reward-based scheduling, we further prove that, when the reward functions are convex, the problem becomes NP-Hard. Our static optimal solution, besides providing considerable reward improvements over the previous suboptimal strategies, also has a major practical benefit. Run-time overhead is eliminated and existing scheduling disciplines may be used without modification with the computed optimal service times View full abstract»

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  • Cellular automata-based recursive pseudoexhaustive test pattern generator

    Publication Year: 2001 , Page(s): 177 - 185
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    This paper presents a recursive technique for generation of pseudoexhaustive test patterns. The scheme is optimal in the sense that the first 2k vectors cover all adjacent k-bit spaces exhaustively. It requires substantially less hardware than the existing methods and utilizes the regular, modular, and cascadable structure of local neighborhood Cellular Automata (CA), which is ideally suited for VLSI implementation. In terms of XOR gates, this approach outperforms earlier methods by 15 to 50 percent. Moreover, test effectiveness and hardware requirements have been established analytically, rather than by simple simulation and logic minimization View full abstract»

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  • Java runtime systems: characterization and architectural implications

    Publication Year: 2001 , Page(s): 131 - 146
    Cited by:  Papers (15)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (780 KB) |  | HTML iconHTML  

    The Java Virtual Machine (JVM) is the cornerstone of Java technology and its efficiency in executing the portable Java bytecodes is crucial for the success of this technology. Interpretation, Just-in-Time (JIT) compilation, and hardware realization are well-known solutions for a JVM and previous research has proposed optimizations for each of these techniques. However, each technique has its pros and cons and may not be uniformly attractive for all hardware platforms. Instead, an understanding of the architectural implications of JVM implementations with real applications can be crucial to the development of enabling technologies for efficient Java runtime system development on a wide range of platforms. Toward this goal, this paper examines architectural issues from both the hardware and JVM implementation perspectives. The paper starts by identifying the important execution characteristics of Java applications from a bytecode perspective. It then explores the potential of a smart JIT compiler strategy that can dynamically interpret or compile based on associated costs and investigates the CPU and cache architectural support that would benefit JVM implementations. We also study the available parallelism during the different execution modes using applications from the SPECjvm98 benchmarks. At the bytecode level, it is observed that less than 5 out of the 256 bytecodes constitute 90 percent of the dynamic bytecode stream. Method sizes fall into a trinodal distribution with peak of 1, 9, and 26 bytecodes across all benchmarks. The architectural issues explored in this study show that, when Java applications are executed with a JIT compiler, selective translation using good heuristics can improve performance, but the saving is only 10-15 percent at best. The instruction and data cache performance of Java applications are seen to be better than that of C/C++ applications except in the case of data cache performance in the JIT mode. Write misses resulting from installation of JIT compiler output dominate the misses and deteriorate the data cache performance in JIT mode. A study on the available parallelism shows that Java programs executed using JIT compilers have parallelism comparable to C/C++ programs for small window sizes, but falls behind when the window size is increased. Java programs executed using the interpreter have very little parallelism due to the stack nature of the SVM instruction set, which is dominant in the interpreted execution mode. In addition, this work gives revealing insights and architectural proposals for designing an efficient Java runtime system View full abstract»

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  • Decision diagram method for calculation of pruned Walsh transform

    Publication Year: 2001 , Page(s): 147 - 157
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB) |  | HTML iconHTML  

    Discrete Walsh transform is an orthogonal transform often used in spectral methods for different applications in signal processing and logic design. FFT-like algorithms make it possible to efficiently calculate the discrete Walsh spectrum. However, for their exponential complexity, these algorithms are practically unsuitable for large functions. For this reason, a Binary Decision Diagram (BDD) based recursive method for Walsh spectrum calculation has been introduced in Clarke et al. (1993). A disadvantage of this algorithm is that the resulting Multi-Terminal Binary Decision Diagram (MTBDD) representing the Walsh spectrum for f can be large for some functions. Another disadvantage turns out if particular Walsh coefficients are to be computed separately. The algorithm always calculates the entire spectrum and, therefore, it is rather inefficient for applications where a subset of Walsh spectral coefficients, i.e., the pruned Walsh spectrum, is required. In this paper, we propose another BDD-based method for Walsh spectrum calculation adapted for application where the pruned Walsh spectrum is needed. The method takes advantage of the property that for most switching functions, the size of a BDD for f is usually quite a bit smaller than the size of the MTBDD for the Walsh spectrum. In our method, a MTBDD representing the Walsh spectrum is not: constructed. Instead, two additional fields are assigned to each node in the BDD for the processed function f. These fields are used to store the results of intermediate calculations. Pairs of spectral coefficients are calculated and stored in the fields assigned to the root node. Therefore, the calculation complexity of the proposed algorithm is proportional to the size of the BDD for f whose spectrum is calculated. Experimental results demonstrate the efficiency of the approach View full abstract»

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  • Hierarchical diagnosis of identical units in a system

    Publication Year: 2001 , Page(s): 186 - 191
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB) |  | HTML iconHTML  

    A hierarchical diagnosis algorithm is presented for testing identical units in a system. As all units are similar, it is essential that the test process be parallelized to enable test of multiple units for the cost of testing one unit. With this objective in mind, we propose a novel test architecture consisting of a hierarchy of testers in a system to test all the units simultaneously. In this approach, special test chips are placed at strategic locations in a system to compute a “golden response” by analyzing the responses of all units. The responses are propagated up the hierarchy of testers. At each level, the testers analyze the data and pass golden response computation data to testers at higher level. The tester at the top of the hierarchy computes the golden response and the test result is percolated down to the testers at the lowest level that identify faulty and fault-free units. Using this diagnosis approach, almost all units are correctly diagnosed, even when yields are as low as 40 percent. The hardware architecture of all test chips is identical and simple. This approach can be used for testing massively parallel multiprocessor systems, MCMs fabricated on a large area panel, and integrated circuits on silicon wafers View full abstract»

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  • Lossless trace compression

    Publication Year: 2001 , Page(s): 158 - 173
    Cited by:  Papers (15)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (900 KB) |  | HTML iconHTML  

    The tremendous storage space required for a useful data base of program traces has prompted a search for trace reduction techniques. In this paper, we discuss a range of information-lossless address and instruction trace compression schemes that can reduce both storage space and access time by an order of magnitude or more, without discarding either references or interreference timing information from the original trace. The PDATS family of trace compression techniques achieves trace coding densities of about six references per byte. This family of techniques is now in use as the standard in the NMSU TraceBase, an extensive trace archive that has been established for use by the international research and teaching community View full abstract»

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  • On codes identifying vertices in the two-dimensional square lattice with diagonals

    Publication Year: 2001 , Page(s): 174 - 176
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB) |  | HTML iconHTML  

    Fault diagnosis of multiprocessor systems motivates the following graph-theoretic definition. A subset C of points in an undirected graph G=(V, E) is called an identifying code if the sets B(v)∩C consisting of all elements of C within distance one from the vertex v are different. We also require that the sets B(v)∩C are all nonempty. We take G to be the infinite square lattice with diagonals and show that the density of the smallest identifying code is at least 2/9 and at most 4/17 View full abstract»

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  • The maximum factor queue length batching scheme for video-on-demand systems

    Publication Year: 2001 , Page(s): 97 - 110
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (460 KB) |  | HTML iconHTML  

    In a video-on-demand environment, batching of video requests is often used to reduce I/O demand and improve throughput. Since viewers may defect if they experience long waits, a good video scheduling policy needs to consider not only the batch size but also the viewer defection probabilities and wait times. Two conventional scheduling policies for batching are the first-come-first-served (FCFS) policy, which schedules the video with the longest waiting request, and the maximum queue length-(MQL) policy, which selects the video with the maximum number of waiting requests. Neither of these policies leads to entirely satisfactory results. MQL tends to be too aggressive in scheduling popular videos by considering only the queue length to maximize batch size, while FCFS has the opposite effect by completely ignoring the queue length and focusing on arrival time to reduce defection. In this paper, we introduce the notion of factored queue length and propose a batching policy that schedules the video with the maximum factored queue length. We refer to this as the MFQL policy. The factored queue length is obtained by weighting each video queue length with a factor which is biased against the more popular videos. An optimization problem is formulated to solve for the best weighting factors for the various videos. We also consider MFQL implementation issues. A simulation is developed to compare the proposed MFQL variants with FCFS and MQL. Our study shows that MFQL yields excellent empirical results in terms of standard performance measures such as average latency time, defection rates, and fairness View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org