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Computers and Digital Techniques, IEE Proceedings E

Issue 4 • Date Jul 1990

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Displaying Results 1 - 13 of 13
  • Efficient linear and bilinear arrays for matrix triangularisation with partial pivoting

    Publication Year: 1990 , Page(s): 295 - 300
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (440 KB)  

    The paper presents two VLSI arrays for implementing Gaussian elimination with partial pivoting. The first is a bilinear array that uses 2n+1 PEs and triangularises an n*n dense matrix in n2+n-2 time units. The second array is a switchable linear array. It uses n PEs to triangularise the n*n dense matrix in 2n2-2n+1 time units. Both arrays use strictly local communications and... View full abstract»

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  • Design and analysis of VLSI-based parallel multipliers

    Publication Year: 1990 , Page(s): 328 - 336
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (496 KB)  

    A design of a parallel multiplier is presented in which the time-consuming multiplication process is recursively decomposed into simple summation processes that can be executed simultaneously. At each recursive step, each and multiplicand is partitioned into four groups of bits and produces 16 partial product terms. An efficient summation process of adding up these partial product terms is propose... View full abstract»

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  • Transputer link reconfiguration: switching networks for 4-valent graphs

    Publication Year: 1990 , Page(s): 239 - 244
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (524 KB)  

    The paper describes the development and implementation of a novel transputer link switching network based on an Eulerian cycle decomposition of a graph of transputer link connections. This network provided completely universal routing of all transputer graphs and multigraphs. The switch settings can be constructed in a time linear in the number of processors. It is shown how the network can be ext... View full abstract»

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  • Boundary segmentation and parameter estimation for industrial inspection

    Publication Year: 1990 , Page(s): 319 - 327
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (664 KB)  

    The paper addresses a typical industrial inspection problem, namely the online estimation of centres and radii of circular arcs on a digitised boundary. The problem is identified as two subproblems: (a) accurate location of knot points where different primitives join, and (b) accurate estimation of parameters related to each segment. The first problem is solved by developing a powerful tool for id... View full abstract»

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  • Performance of banyan networks with inhomogeneous traffic flow

    Publication Year: 1990 , Page(s): 245 - 252
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (628 KB)  

    To date, most research results regarding the performance of banyan networks assumed a uniform traffic model. Sources are assumed to generate connection requests independently with the same rate and, moreover, connection requests are assumed to be independently and equally likely destined to each destination. This assumption, which greatly simplifies analysis, may not be true for real-world systems... View full abstract»

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  • Distributive implementation of relational operations

    Publication Year: 1990 , Page(s): 283 - 294
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1192 KB)  

    Like sorting algorithms, implementations of relational database operations can either be comparative or distributive or a hybrid of these. Relational intersection, natural join and union operations can be implemented distributively by bitwise Boolean operations on bit matrices that are superimposed coded representations of operand relations. A bitwise AND or OR operation yields a further bit matri... View full abstract»

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  • Symmetric degree-four chordal ring networks

    Publication Year: 1990 , Page(s): 310 - 318
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (696 KB)  

    Techniques for analysing symmetric chordal ring networks of degree four are presented and expressions for the network diameter and the mean internode distance are derived. The network incorporates the maximum number of nodes for a given diameter, and has a communications cost, measured either as network diameter or as the mean internode distance, of O( square root (N)). Possible modifications to t... View full abstract»

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  • GM-Learn: an iterative learning algorithm for CMOS gate matrix layout

    Publication Year: 1990 , Page(s): 301 - 309
    Cited by:  Papers (6)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (772 KB)  

    An iterative CMOS gate matrix layout algorithm utilising artificial intelligence (A.I.) learning techniques is proposed. This algorithm called GM-Learn, features a rudimentary learning mechanism which enables iterative improvements of the quality of a gate matrix layout. This accomplished through the repetitive applications of a one-pass gate matrix layout algorithm, called GM-Plan, to realise a g... View full abstract»

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  • Built-in self-test structures around cellular automata and counters

    Publication Year: 1990 , Page(s): 269 - 276
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (624 KB)  

    BIST structures for on-chip generation of random, exhaustive and deterministic test patterns have been discussed in the paper. Isomorphism between maximal length LFSR (linear feedback shift register) and exhaustive CA has been established and the pseudorandomness properties of CAs in terms of well-suited autocorrelation functions have been investigated. Owing to the regularity in interconnection s... View full abstract»

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  • A comparative architectural study of three MIMD computing surfaces

    Publication Year: 1990 , Page(s): 261 - 268
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (592 KB)  

    The performance of three MIMD message-passing computing surfaces have been investigated in the paper. These three computing surfaces are the augmented torus, the torus and the grid-bus. The three computing surfaces are closely related in hardware implementation. First, the generalised stochastic Petri nets (GSPN) model has been used to predict the performance of the three computing surfaces probab... View full abstract»

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  • Pragmatic approach to systolic design

    Publication Year: 1990 , Page(s): 277 - 282
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (600 KB)  

    Limitations of current systolic designs are pointed out and new constraints are imposed to make systolic solutions practical. Matrix multiplication is used as an illustration, and a simple but very high performance systolic architecture, the supercoprocessor for matrix problems (S-MP), which satisfies these constraints is presented. Implementation alternatives for the linear systolic array for mat... View full abstract»

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  • A 'delayed layering' three layer channel routing

    Publication Year: 1990 , Page(s): 229 - 238
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (844 KB)  

    A new three-layer channel router with 'delayed layering' technique is presented. The delayed layering scheme in the routing can improve the capability of the router to reach comprehensive objectives. This new router not only minimises the tracks used, but also minimises the via usage and maximises the use of preferred routing layers. The delayed layering router consists of two steps: track assignm... View full abstract»

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  • Multidimensional fast Fourier transform into SIMD hypercubes

    Publication Year: 1990 , Page(s): 253 - 260
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (652 KB)  

    The paper presents the in-place implementation of the multidimensional radix 2 fast Fourier transform (FFT), along with the corresponding algorithm for data shuffling (bit-reversal) on SIMD hypercube computers. Each processor possesses its own non-shared memory, the number of processors being less than or equal to the number of data. The flexibility of the proposed algorithm is based on the scheme... View full abstract»

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