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Computers, IEEE Transactions on

Issue 5 • Date May 1990

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Displaying Results 1 - 17 of 17
  • Practical cellular dividers

    Page(s): 605 - 614
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB)  

    A discussion is presented of parallel division algorithms that can be classified among modified higher radix nonrestoring online division methods, where redundant representations are extensively utilized to speed up the operation. The network realizations of these algorithms are cellular, or even systolic with exclusively local control; they have both size (area) and time of O(n), where n is the length of the dividend representation. The same structures can also be used as a signed, digit-serial multiplier. When suitably equipped with some control and a few registers, the divider/multiplier brings remarkable performance to large modular arithmetic, RSA cryptography, and greatest common divisor computations. They are also of interest for the design of floating-point units and signal processing applications View full abstract»

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  • Cost reduction in the CCD realization of MVMT functions

    Page(s): 702 - 706
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    The cost effectiveness of using an overflow circuit for truncated difference operation and a metal line for charge replication in the charge-coupled device (CCD) realization of multivalue multithreshold (MVMT) functions is considered. It is shown that the use of these two circuits leads to improved realizations compared to those achieved by previous approaches View full abstract»

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  • An approach to implementing multiplication with small tables

    Page(s): 717 - 718
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    Table look-up is an attractive approach to implementing multiplication; however, the size of the requisite multiplication table is prohibitively large for wide operands. A novel transformation which reduces the number of table entries from 22b to 2b, where b is the width of the operands, is presented. Two implementation schemes are presented View full abstract»

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  • Unifying maximum cut and minimum cut of a planar graph

    Page(s): 694 - 697
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    The real-weight maximum cut of a planar graph is considered. Given an undirected planar graph with real-value weights associated with its edges, the problem is to find a partition of the vertices into two nonempty sets such that the sum of the weights of the edges connecting the two sets is maximum. The conventional maximum cut and minimum cut problems assume nonnegative edge weights, and thus are special cases of the real-weight maximum cut. An O(n3/2 log n) algorithm for finding a real-weight maximum cut of a planar graph where n is the number of vertices in the graph is developed. The best maximum cut algorithm previously known for planar graphs has running time of O(n3) View full abstract»

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  • Area-time optimal adder design

    Page(s): 666 - 675
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    A systematic method of implementing a VLSI parallel adder is presented. A family of adders based on a modular design is defined. The design uses three types of component cells, which are implemented in static CMOS. The adder design is formulated as a dynamic programming problem, optimizing with respect to area and time. The result is an area-time optimal adder in the design family. The approach is illustrated by implementing a 66-bit adder for use in a floating-point processor. It is shown how to use the method for implementations in technologies and design styles other than static CMOS View full abstract»

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  • Sorting n objects with a k-sorter

    Page(s): 714 - 716
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    A k-sorter is a device that sorts k objects in unit time. The complexity of an algorithm that uses a k-sorter is defined as the number of applications of the k-sorter. In this measure, the complexity of sorting n objects is between n log n/k log k and 4n log n/k log k, up to first-order terms in n and k View full abstract»

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  • Performance evaluation of a dataflow architecture

    Page(s): 615 - 627
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    The formulation and validation of an analytical approach for the performance evaluation of the Manchester dataflow computer is discussed. The analytical approach is based on closed queuing network models. The average parallelism of the dataflow graph being executed on the dataflow architecture is shown to be related to the population of the closed network. The model of the dataflow computer is validated by comparing the analytical results to those obtained from the prototype Manchester dataflow computer and from simulation. The bottleneck centers in the prototype machine have been identified through the model, and various architectural modifications have been investigated from performance considerations View full abstract»

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  • Improvements to an algorithm for equipartitioning

    Page(s): 706 - 710
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    Modifications to a clustering algorithm in which objects are adaptively partitioned into clusters of equal size are described. The object migration automaton has the advantage of being conceptually simple and easy to implement. Unfortunately, the algorithm may exhibit slow convergence speed and in some cases may not converge at all. The algorithm is modified to provide remedies to these conditions. Through experimental results, the modifications are shown to yield a substantial speedup in convergence (while maintaining 100% accuracy), especially as the number of objects to be partitioned increases View full abstract»

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  • Analysis of self-stabilizing clock synchronization by means of stochastic Petri nets

    Page(s): 597 - 604
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    A model for analyzing a FCS (fault-tolerant clock synchronization) system of the type supported by a statistical self-diagnosis is described. Once a self-diagnosis scheme is integrated into an FCS design, the problem of controlling and measuring the system's self-stability arises. A stochastic Petri net (SPN) model is constructed to derive the self-stability measures of such FCS systems. An example is given to demonstrate the entire modeling and analyzing procedure. The mapping from SPN model to Markov model shown in an example can be automated by using an SPN software package. The results show that the SPN model is an excellent tool for obtaining self-stability measures and that several important system features, such as synchronization and parallelism, can be modeled using the SPN method in a much clearer manner than they can be modeled using other available tools View full abstract»

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  • Half-hot state assignments for finite state machines

    Page(s): 700 - 702
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    The state assignment problem for the programmable logic array (PLA) implementation of finite state machines is considered. It is pointed out that the number of PLA columns can be reduced by using state assignments leading to logic that is unate in the state variables. Half-hot state assignments are proposed, where each state has an encoding in which exactly half the state variables are equal to 1 View full abstract»

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  • Emulation of hypercube architecture on nearest-neighbor mesh-connected processing elements

    Page(s): 698 - 700
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    The problem of emulating a hypercube architecture on nearest-neighbor mesh (NNM) connected processing elements is addressed. The motivation for this study was the recent promotion of the transputer as a possibly very powerful building block of large highly parallel, scalable computer architectures. It is an attempt to achieve hypercubes of different dimensions with a constant, small number of links per processing element. The idea was investigated by means of some less abstract ways of reasoning and computer simulation in an attempt to find the best form of NNM connected processing element structures form the viewpoint of the optimization of certain parameters of the emulated hypercube View full abstract»

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  • Systolic evaluation of polynomial expressions

    Page(s): 653 - 665
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    Two types of organizations are presented for frame buffers of m×m pixels: one is a single wavefront complex cell array requiring O(m2n) space and the other is a simple cell multiple wavefront array with O( m2) area and O(n2) wavefronts. Both these organizations have two main advantages over an earlier method: the cells and the interconnection among them are regular and hence are suitable for efficient VLSI implementation, and the organization permits evaluation of higher-order polynomials View full abstract»

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  • Finding the optimal variable ordering for binary decision diagrams

    Page(s): 710 - 713
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    The ordered binary decision diagram is a canonical representation for Boolean functions, presented by R.E. Bryant (1985) as a compact representation for a broad class of interesting functions derived from circuits. However, the size of the diagram is very sensitive to the choice of ordering on the variables; hence, for some applications, such as differential cascode voltage switch (DCVS) trees, it becomes extremely important to find the ordering leading to the most compact representation. An algorithm for this problem with time complexity O (n23n) is presented. This represents an improvement over the previous best algorithm View full abstract»

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  • A distributed commit protocol for a multicomputer system

    Page(s): 718 - 724
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (668 KB)  

    A distributed commit protocol suitable for multicomputer systems is described. A general programming environment which provides transactions as a programming tool is discussed. This environment is expected to be more dynamic than a database management system; in particular, it is not known how many and which processes will participate in a specific transaction. Therefore, a model of completely distributed transactions, without any hierarchical structure among the participant processes or any centralized locus of control, is proposed View full abstract»

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  • Easily testable iterative logic arrays

    Page(s): 640 - 652
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    Iterative logic arrays (ILAs) are studied with respect to two testing problems. First, a variety of conditions is presented. Meeting these conditions guarantees an upper bound on the size of the test set for the ILA under consideration. Second, techniques for designing optimally testable ILAs are presented. The arrays treated are, in some cases, more general than those that have been reported by other researchers: they include multidimensional and inhomogeneous arrays. Octagonally connected arrays and bilateral arrays are also discussed. The results indicate that the characteristics of the individual cell functions (e.g. whether they are bijective) are a good guide to the test complexity of the overall array. Matrix multiplication, as an example, is shown to have several different optimally testable implementations. The results are useful for combinational and pipelined arrays and for certain systolic arrays View full abstract»

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  • Optimal VLSI dictionary machines without compress instructions

    Page(s): 676 - 693
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    Several designs are presented for VLSI dictionary machines that combine both a linear (modify) network and a logarithmic (query) network with a novel idea for separation of concerns. The initial design objectives included: (1) single-cycle operability of host-issued modify and query commands (no compress instructions), (2) complete processor utilization (no waste processors), and (3) optimal 2 log n response times, where n is the current population of the machine. The authors sought simple ideas that, for the first time, would allow all three objectives to be achieved simultaneously. They were forced to abandon objective (3), instead achieving a slightly weaker objective, namely, near-optimal (2 log n+R) response times, where R is the time for a round trip through the particular prenetwork used to connect the host to the roots of the query trees in the logarithmic network. Both sorted and unsorted versions of dictionary machines are presented. Those with orthogonal command networks achieve all objectives; those without orthogonal networks achieve only the first and third View full abstract»

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  • A communicating finite automata approach to modeling distributed computation and its application to distributed decision-making

    Page(s): 628 - 639
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1180 KB)  

    A modeling technique for distributed computation based on a combination of directed graphs and finite automata is described. The paradigm of distributed decision-making (DDM) is used to illustrate the technique for its two primary purposes: providing a standard specification mechanism for different algorithms for solving the same problem and providing a common mechanism for objective quantitative evaluation and comparison of alternative DDM algorithms. This is accomplished through the definition of the terms performance and efficiency as they relate to the domain of DDM. The two terms, which have precise meanings with respect to the analysis of sequential algorithms, currently lack a common interpretation in the environment of DDM. In particular, they need to be expressed in terms of the information movement necessary to share state information. The method has been used extensively to conduct analyses of several distribution scheduling algorithms. This paper focuses on the model specification properties View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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