By Topic

Semiconductor Manufacturing, IEEE Transactions on

Issue 4 • Date Nov. 2000

Filter Results

Displaying Results 1 - 14 of 14
  • Author index

    Page(s): 497 - 499
    Save to Project icon | Request Permissions | PDF file iconPDF (31 KB)  
    Freely Available from IEEE
  • Sujbect index

    Page(s): 499 - 506
    Save to Project icon | Request Permissions | PDF file iconPDF (62 KB)  
    Freely Available from IEEE
  • A study on ℜm→ℜ1 maps: application to a 0.16-μm via etch process endpoint

    Page(s): 457 - 468
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    We introduce several endpoint algorithms that map real-time, in situ process signals to a via etch process endpoint. Some of the mathematical techniques include: Andrews plots (Fourier series), Chebyshev polynomials, Legendre polynomials, wavelets, singular value decomposition, and neural networks. We show that many of the techniques work to varying degrees of success for a via etch process on 0.16-μm technology. Based on our observations from many lots of manufacturing wafers and experiments with all the endpoint methods, we believe the Chebyshev polynomial area-time curves perform the best, but this statement should be taken with a caveat. It is really best to empirically test the various methods for a given etch process to deduce the endpoint algorithm for that application View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of the impact of process variations on clock skew

    Page(s): 401 - 407
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as VT and IDSS, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Intelligent quality controllers for on-line parameter design

    Page(s): 481 - 491
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    Parameter design methods, in general, do not take into account the common occurrence that some of the uncontrollable factors are observable for products and processes, during operation and production, respectively. This paper introduces a methodology that facilitates on-line parameter design for products and processes utilizing the extra information available about observable uncontrollable factors. Implementation of the proposed methodology leads to a quality controller that operates in two distinct modes: identification mode and on-line parameter design mode, identification mode involves establishing a model that relates quality response characteristics with significant controllable and uncontrollable variables. On-line parameter design mode involves optimization of the controllable variables with respect to desired levels of output quality parameters, with consideration to levels of the observable uncontrollable variables. A plasma etching semiconductor manufacturing process is used as a testbed for the proposed intelligent quality controllers. Results reveal that the proposed quality controllers can be used for on-line parameter design of manufacturing processes. Results also reveal that significant improvements in quality (measured in terms of average deviation of process outputs from target) over off-line parameter design approaches are to be expected in production processes with some level of control on uncontrollable variables. Even in the absence of any control on uncontrollable variables, the proposed controllers always perform better than traditional off-line robust parameter design techniques; however, the improvements may not be significant View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Real-time control of reactive ion etching using neural networks

    Page(s): 469 - 480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    This paper explores the use of neural networks for real-time, model-based feedback control of reactive ion etching (RIE). This objective is accomplished in part by constructing a predictive model for the system that can be approximately inverted to achieve the desired control. An indirect adaptive control (IAC) strategy is pursued. The IAC structure includes a controller and plant emulator, which are implemented as two separate back-propagation neural networks. These components facilitate nonlinear system identification and control, respectively. The neural network controller is applied to controlling the etch rate of a GaAs/AlGaAs metal-semiconductor-metal (MSM) structure in a BCl3/Cl2 plasma using a Plasma Therm 700 SLR series RIE system. Results indicate that in the presence of disturbances and shifts in RIE performance, the IAC neural controller is able to adjust the recipe to match the etch rate to that of the target value in less than 5 s. These results are shown to be superior to those of a more conventional control scheme using the linear quadratic Gaussian method with loop-transfer recovery, which is based on a linearized transfer function model of the RIE system View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel filtering method to extract three critical yield loss components (gross, repeated, and random) FIMER

    Page(s): 408 - 415
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    This paper describes a novel filtering method (FIMER) to extract three critical yield loss components: gross yield loss from parametric problems or from clustering of defects, repeated yield loss from mask defects or from lithography margin, and random yield loss mainly from particles. It is shown by simulation that FIMER is not only superior to the conventional windowing method in extracting repeated yield loss but also accurately extracts gross yield loss and random yield loss. The simulation studies show that the three components are extracted with an error equal to or less than 5% by optimizing threshold and filter weights, which are the major parameters in FIMER View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reducing airborne molecular contamination by efficient purging of FOUPs for 300-mm wafers-the influence of materials properties

    Page(s): 427 - 433
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    The control of airborne molecular contamination (AMC) plays an increasing role in semiconductor manufacturing processes. A method to reduce AMC is purging of wafer boxes with inert gas. In this study, data on the practicability and optimization of purging a front opening unified pod (FOUP), a wafer box for 300-mm wafers, are presented. Different parameters for the purge process are evaluated experimentally. Key values for the assessment of efficiency are the time-dependent content of oxygen and humidity in the FOUP. The increase in the key values after the purge was measured and the construction of the FOUP was modified in order to obtain sufficient tightness. Spatially resolved measurements reveal the homogeneity of the purge. Experimental data are compared to data obtained by a simulation using a computational fluid dynamics program. Values for oxygen are in agreement with the calculated curves. In contrast to this, an additional, long-lasting contribution that was not taken into account in the simulations makes depletion of humidity slower than expected. This contribution is explained with the desorption and permeation of humidity through the plastic walls of the FOUP. The presence of both effects, desorption and permeation, is proved and quantified. Materials properties turn out to heavily affect purge effectiveness and the postpurge ingress of certain contaminants in a wafer box View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thermal uniformity of 12-in silicon wafer during rapid thermal processing by inverse heat transfer method

    Page(s): 448 - 456
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326°C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Derivation of a nonlinear variance equation and its application to SOI technology

    Page(s): 492 - 496
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    An analytic nonlinear equation for variance was derived along with a method based on response surface mapping techniques to calculate the variance using the proposed equation. The technique was applied to the threshold voltage of a 0.1-μm silicon-on-insulator MOS device, and the variance value obtained was verified using Monte Carlo simulation. The threshold voltage dependence upon active-layer thickness was found to be highly nonlinear due to the device's going from the fully depleted to the partially depleted regime. Analysis of the variance showed that the effect of the nonlinear terms (18.7%) is more important than the effect of the mixed term (-0.7%) and almost as important as the contribution of the second most dominant input-process parameter (23.6%). This illustrates the importance of the proposed nonlinear equation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Calibration of a two-dimensional numerical model for the optimization of LOGOS-type isolations by response surface methodology

    Page(s): 416 - 426
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (736 KB)  

    The models used for process simulation have to be carefully calibrated in order to insure a correct prediction of the topography and doping/stress profiles of microelectronic devices. With the current miniaturization of these devices, the requirements on the accuracy of the simulated results become greater, which puts more constraints on the calibration methodology. This is particularly the case for the silicon oxidation model, which is involved in numerous fundamental steps of an industrial process. In this paper, using response surface methodology, a viscoelastic oxidation model has been calibrated on a wide range of process conditions, which has allowed the optimization of LOCOS-type isolation structures for a 0.35-μm CMOS technology View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Scalability study of laser-induced vertical make-link structure

    Page(s): 442 - 447
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (108 KB)  

    The scalability of a direct metal-to-metal connection between two different levels of metallizations has been extrapolated to be compatible with modern semiconductor fabrication technology. A simple equation to evaluate the scalability was formulated based on focused ion beam (FIR) cross-sectional images of larger link structures with various sizes. With a 0.6-μm-thick metal 1 line and a 0.5-μm-thick interlevel dielectric (ILD), a width of less than 0.5 μm is evaluated to be possible for the metal 1 line. Two limitations exist in the process of scaled-down link structures, which are the ratio of the thickness of ILD to the thickness of the metal 1 line, tILD/t m, and the quality of laser beam parameters including the spot size and positioning error. However, modern processing technologies and advanced laser processing systems are considered to allow the scalability of a vertical make-link structure. Two layouts of two-level interconnects were designed with increased interconnect densities with a 1-μm pitch of a 0.5-μm-wide metal 1 line. These results demonstrate the application of commercially viable vertical linking technology to very large-scale integration (VLSI) applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Capture rate enhance method of 0.1-μm level defects by pattern-matching inspectors

    Page(s): 434 - 441
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    In this paper, a method of enhancing the capture rate of 0.1-μm level defects by pattern-matching inspectors is studied from the viewpoint of image variances. By our method, defect inspection engineers can obtain quantitative information for enhancing the capture rate of 0.1-μm level defects on both actual devices and test element groups (TEGs). The inspection sensitivities were experimentally evaluated by using the detection rate of the defects on an actual device and on the TEG. The image noise and the defect signal of the captured charge-coupled device (CCD) images of the same defect were quantitatively analyzed. The observed image noise and the defect signal obey a normal distribution. The capture rate calculated by our model, based on normal distribution, almost agrees with the experimental data. Next, we propose a new criterion called the “practical rapture rate” by uniting the rapture rate and the false count. The threshold value optimized from the viewpoint of the practical capture rate agrees with empirical thresholds value set by our defect inspection engineers. Finally, as an example of capture rate enhancement, a unique TEG called TWICE (TEG with image contrast enhancing) for photoresist inspection is demonstrated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of parameter variations at chip and wafer level on clock skews

    Page(s): 395 - 400
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    In this paper, a methodology is proposed to determine clock skews and the performance of clock architectures considering parameter variations in an early stage of technology development. With this methodology, it is possible to separate process-induced clock skew from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future. By comparing a 0.45- and a 0.25-μm technology, it is shown that in the future, process variations will increase clock skew. The clock skews are determined by measuring the relevant device and metal line parameters as a function of position over chip and wafer. In the past, parameters like IDS, Vth, and resistances could be measured very precisely, although it was difficult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect capacitances extremely precisely. Based on these measurement data, a netlist of a defined clock tree is created by a C-program, and the clock signal delay is simulated. From the delay simulation, we calculate the clock skew for each chip dependent on the parameter variations. Experimental results are separated into a basic random fluctuation part and processing-related contributions on the chip and wafer levels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clocktree but allows investigation of all kinds of clock distribution circuits. The method has clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costly measurement of signal delays by voltage contrast methods is required, since all parameters are determined by measurement on the device level View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721