By Topic

Solid-State Circuits, IEEE Journal of

Issue 12 • Date Dec. 2000

Filter Results

Displaying Results 1 - 25 of 36
  • Guest Editorial

    Page(s): 1756 - 1759
    Save to Project icon | Request Permissions | PDF file iconPDF (41 KB)  
    Freely Available from IEEE
  • A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-/spl mu/m digital CMOS process

    Page(s): 1760 - 1768
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    The design of a high-speed analog-to-digital (A/D) converter for hard disk drive read channels is described. The A/D converter uses a flash architecture with an interleaved sample and hold and interpolating comparator pre-amplifiers. It has 6 bits of resolution at full speed as well as a 7 bit mode operating at a lower speed. The 7 bit mode is useful for servo signal processing. This A/D converter has been implemented in a four-level metal single-poly 0.25 /spl mu/m CMOS technology. The device operates at a speed of up to 700 MSamples/s in the 6 bit mode while maintaining a signal-to-noise-plus-distortion rate (SNDR) of greater than 35 dB at input frequencies of up to one-fourth the sampling rate. In the 7 bit mode, the device operates at up to 200 MSamples/s with a SNDR greater than 41 dB. It occupies an active area of 0.45 mm/sup 2/ and consumes less than 187 mW of power. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR

    Page(s): 1769 - 1780
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (333 KB)  

    A 12-b analog-to-digital converter (ADC) is optimized for spurious-free dynamic range (SFDR) performance at low supply voltage and suitable for use in modern wireless base stations. The 6-7-b two-stage pipeline ADC uses a bootstrap circuit to linearize the sampling switch of an on-chip sample-and-hold (S/H) and achieves over 80-dB SFDR for signal frequencies up to 75 MHz at 50 MSample/s (MSPS) without trimming, calibration, or dithering. INL is 1.3 LSB, differential nonlinearity (DNL) is 0.8 LSB. The 6-b and 7-b flash sub-ADCs are implemented efficiently using offset averaging and analog folding. In 0.6-/spl mu/m CMOS, the 16-mm/sup 2/ ADC dissipates 850 mW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming

    Page(s): 1781 - 1790
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (206 KB)  

    Two key concepts of pipelining and background offset trimming are applied to demonstrate a 13-b 40-MSamples/s CMOS analog-to-digital converter (ADC) based on the basic folding and interpolation architecture. Folding amplifier stages made of simple differential pairs are pipelined using distributed interstage track-and-holders. Background offset trimming implemented with a highly oversampling delta-sigma modulator enhances the resolution of the CMOS folders beyond 12 bits. The background offset trimming circuit continuously measures and adjusts the offsets of the folding amplifiers without interfering with the normal operation. The prototype system is further refined using subranging and digital correction, and exhibits a spurious-free dynamic range (SFDR) of 82 dB at 40 MSamples/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are about /spl plusmn/0.5 and /spl plusmn/2.0 LSB, respectively. The chip fabricated in 0.5-/spl mu/m CMOS occupies 8.7 mm/sup 2/ and consumes 800 mW at 5 V. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 14-bit 100-Msample/s subranging ADC

    Page(s): 1791 - 1798
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (189 KB)  

    This paper describes a 14-b analog-to-digital converter designed in a complementary bipolar process. Although it uses a fairly traditional three-stage subranging architecture, several nontraditional techniques are incorporated to achieve 14 bits of performance at a clock rate of 100 MHz. For linearity, the most critical of these is wafer level trimming of the first subrange digital-to-analog converter. Prototype silicon exhibits a spurious-free dynamic range of 90 dB through the Nyquist frequency and a signal-to noise ratio of 74 dB while dissipating 1.25 W. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A two-path bandpass sigma-delta modulator with extended noise shaping

    Page(s): 1799 - 1809
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (169 KB)  

    A three-stage bandpass sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-/spl mu/m CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f/sub s//4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm/sup 2/. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10.7-MHz IF-to-baseband /spl Sigma//spl Delta/ A/D conversion system for AM/FM radio receivers

    Page(s): 1810 - 1819
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB)  

    /spl Sigma//spl Delta/ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time /spl Sigma//spl Delta/ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm/sup 2/ in 0.25-/spl mu/m standard digital CMOS. The /spl Sigma//spl Delta/ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio

    Page(s): 1820 - 1828
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (179 KB)  

    A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8/spl times/ oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm/sup 2/ chip in 0.5-/spl mu/m CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC

    Page(s): 1829 - 1840
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (295 KB)  

    The design of a multibit /spl Delta//spl Sigma/ converter is presented. It uses a third-order 4-bit /spl Delta//spl Sigma/ topology with data weighted averaging (DWA) to reduce the linearity requirements of the digital-to-analog converters in the feedback loop. The implementation of the DWA algorithm is optimized to minimize the delay introduced in the feedback loop, resulting in clock frequencies up to 100 MHz. Behavioral models are used to determine several building block specifications. An accurate model is used to analyze the combined effect of the dominant closed loop pole of the operational transconductance amplifier (OTA), the slew rate and the nonzero switch resistance. It is shown that the offset requirements for the quantizer result in a large input capacitance of the quantizer. Therefore scaling of the OTAs, as classically employed in single-bit /spl Delta//spl Sigma/ converters, can no longer be used. For an oversampling ratio of only 24, the converter achieves a signal-to-noise ratio of 95 dB, a signal-to-noise-plus-distortion ratio of 89 dB and an input dynamic range of 97 dB after comb-filtering. The converter is sampled at 60 MHz, resulting in a 2.5 MS/s output rate. It is implemented in a standard 0.65-/spl mu/m CMOS technology, occupies 5.3 mm/sup 2/ and consumes 295 mW from a 5-V power supply. When clocked at 100 MHz with an oversampling ratio of 8, a 12-bit resolution is achieved at an output rate of 12.5 MS/s. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A self-trimming 14-b 100-MS/s CMOS DAC

    Page(s): 1841 - 1852
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB)  

    A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and dynamic linearity is presented. The DAC is based on a central core of 15 thermometer decoded MSBs, 31 thermometer decoded upper LSBs (ULSBs) and 31 binary decoded lower LSBs (LLSBs). The static linearity corresponding to the 14-b specification is obtained by means of a true background self-trimming circuit which does not use additional current sources to replace the current source being measured during self-trimming. The dynamic linearity of the DAC is enhanced by a special track/attenuate output stage at the DAC output which tracks the DAC current outputs when they have settled but attenuates them for a half-clock cycle after the switching instant. The DAC occupies 3.44 mm/spl times/3.44 mm in a 0.35-/spl mu/m CMOS process, and is functional at up to 200 MS/s, with best dynamic performance obtained at 100 MS/s. At 100 MS/s, power consumption is 180 mW from a 3.3-V power supply, and 210 mW at 200 MS/s. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 30-100-MHz NPN-only variable-gain class-AB instantaneous companding filters for 1.2-V applications

    Page(s): 1853 - 1864
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    Two variations of a continuous-time instantaneous companding filter were integrated in a 25 GHz bipolar process. Their -3-dB frequencies are tunable in the ranges of 1-30 and 30-100 MHz. The DC gains are controllable up to 10 dB. The measured dynamic ranges for a 1% total harmonic distortion are 62.5 and 50 dB, for the 30 and 100 MHz filters, respectively. At maximum cutoff frequencies, the filters dissipate 6.5 mW from a 1.2 V supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10.7-MHz CMOS SC radio IF filter using orthogonal hardware modulation

    Page(s): 1865 - 1876
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (229 KB)  

    FM radio receivers require an IF filter for channel selection, customarily set at an IF center frequency of 10.7 MHz. Up until now, the limitations of integrated radio selectivity filters in terms of power dissipation, dynamic range, and cost are such that it is still required to use an external ceramic 10.7-MHz bandpass filter. This paper demonstrates a CMOS switched-capacitor IF filter that can be integrated with most of the rest of the FM receiver, eliminating external components and printed circuit board area. This is made possible through a combination of two techniques: orthogonal hardware modulation, and delta-charge redistribution. It exhibits a tightly controlled center frequency with a Q of 55 and also contains a programmable gain. The filter occupies an area of 0.7 mm/sup 2/ in a 0.6 /spl mu/m CMOS process with poly-poly capacitors. The new filter requires only 16 mW of power, and this is offset by elimination of the power needed in current designs to drive off-chip filters. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A CMOS nested-chopper instrumentation amplifier with 100-nV offset

    Page(s): 1877 - 1883
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (133 KB)  

    A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV. This performance is obtained by nesting an additional low-frequency chopper pair around a conventional chopper amplifier. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. The test chip is free from 1/f noise and has a thermal noise of 27 nV//spl radic/Hz consuming a total supply current of 200 /spl mu/A. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers

    Page(s): 1884 - 1888
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB)  

    A CMOS limiting amplifier with a bandwidth of 3 GHz, a gain of 32 dB, and a noise figure of 16 dB is described. The amplifier is fabricated in a standard 2.5-V 0.25-/spl mu/m CMOS technology and consumes 53 mW. Inversely scaled amplifier stages and active inductors with a low voltage drop are used to achieve this performance. The amplifier is targeted for use in 2.5-Gb/s (OC-48) SONET systems. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A differential 160-MHz self-terminating adaptive CMOS line driver

    Page(s): 1889 - 1894
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    A wide-band differential line driver is presented for transformer-coupled cables integrated in standard 0.35-/spl mu/m CMOS. It achieves 160-MHz bandwidth and no loss in implementing the cable termination. While operating from a 3.3-V supply, the driver dissipates 155 mW and exhibits a -47.5-dB THD for a 2-V/sub pp/ signal across a 75-/spl Omega/ load. Automatically tuned termination and a voltage gain independent of process and load impedance variation are provided by the architecture. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 2-V CMOS cellular transceiver front-end

    Page(s): 1895 - 1907
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-/spl mu/m CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-/spl mu/m CMOS technology, without tuning or trimming. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 2.4-GHz low-IF receiver for wideband WLAN in 6-/spl mu/m CMOS-architecture and front-end

    Page(s): 1908 - 1916
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (241 KB)  

    This paper presents the 2.4-GHz front-end and the first downconversion section of a fully integrated low-IF receiver. The dual-conversion receiver rejects the image repeatably by 60 dB using integrated polyphase filters without calibration or tuning. The gain of the RF mixer and IF amplifier is switchable to slide the available dynamic range of the following stages based on the conditions of the input signal. The front-end and downconversion sections drain 35 mA on average from a 3.3-V supply. Minimum cascade noise figure is 7.2 dB, and maximum cascade IIP3 is -3.4 dBm. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-voltage 5.1-5.8-GHz image-reject receiver with wide dynamic range

    Page(s): 1917 - 1926
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB)  

    A monolithic 5-6-GHz band receiver, consisting of a differential preamplifier, dual doubly balanced mixers, cascaded injection-locked frequency doublers, and a quadrature local oscillator generator and prescaler, realizes over 45 dB of image-rejection in a mature 25-GHz silicon bipolar technology. The measured single sideband (50 /spl Omega/) noise figure is 5.1 dB with an IIP3 of -4.5 dBm and 17-dB conversion gain at 5.3 GHz. The 1.9/spl times/1.2 mm/sup 2/ IC is packaged in a standard 32-pin ceramic quad flatpack and consumes less than 50 mW from a 2.2-V supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 5-GHz CMOS radio transceiver front-end chipset

    Page(s): 1927 - 1933
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (159 KB)  

    Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-/spl mu/m CMOS technology. The 4-mm/sup 2/ 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm/sup 2/ transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high IIP2 downconversion mixer using dynamic matching

    Page(s): 1934 - 1941
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (165 KB)  

    This paper presents an RF downconversion mixer with improved rejection to second-order intermodulation for RF application within a direct-conversion receiver requiring high input blocking performance. The mixer, implemented in a 2.7-V 0.35-/spl mu/m BiCMOS process, achieves a second-order input intercept point of at least +72 dBm for a BiCMOS design and at least +66 dBm for an all-CMOS design. The design utilizes dynamic matching to enhance the balance of a fully differential mixer through mitigation of both component and device mismatches. In addition, dynamic matching is shown to improve the mixer's 1/f noise performance. For an all-CMOS mixer design, a 30-dB improvement in the mixer's noise floor at 1 kHz has been observed compared to conventional fully differential CMOS Gilbert-cell mixer. Additionally, background is given on second-order intermodulation and on system IIP2 requirements for a direct-conversion receiver. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-power low-noise accurate linear-in-dB variable-gain amplifier with 500-MHz bandwidth

    Page(s): 1942 - 1948
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    A linear-in-dB variable-gain amplifier (VGA) using a pre-distortion circuit to generate the gain-control signal is fabricated in a BiCMOS process with f/sub T/=20 GHz. The VGA comprises two cascaded stages of signal-summing VGA and has a variable-gain range of over 70 dB. It can operate at up to 500 MHz and dissipates 36 mW from a 3-V supply. A noise figure of below 5 dB and IIP3 of over -38 dBm at 43-dB gain were obtained. The VGA achieved a gain error of less than 2 dB over 70-dB gain range, and it occupies approximately 1 mm/sup 2/. The VGA is applicable to future code division multiple access (CDMA) receivers. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A fully integrated SiGe receiver IC for 10-Gb/s data rate

    Page(s): 1949 - 1957
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (246 KB)  

    A silicon germanium (SiGe) receiver IC is presented here which integrates most of the 10-Gb/s SONET receiver functions. The receiver combines an automatic gain control and clock and data recovery circuit (CDR) with a binary-type phase-locked loop, 1:8 demultiplexer, and a 2/sup 7/-1 pseudorandom bit sequence generator for self-testing. This work demonstrates a higher level of integration compared to other silicon designs as well as a CDR with SONET-compliant jitter characteristics. The receiver has a die size of 4.5/spl times/4.5 mm2 and consumes 4.5 W from -5 V. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver

    Page(s): 1958 - 1963
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB)  

    This paper presents a single-chip eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver. The IC provides an analog output voltage proportional to the horizontal eye opening of a data signal. The chip includes a delay-locked loop for automatic adjustment of the clock phase. It was designed in a 50-GHz-f/sub T/ SiGe bipolar technology and dissipates 4.95 W from a -5-V supply. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A CMOS HDSL2 analog front-end

    Page(s): 1964 - 1975
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    A 5-V 0.5-/spl mu/m CMOS analog front-end (AFE) IC for HDSL2 incorporates transmit digital-to-analog converter (DAC), transmit filters, output buffer, receive AGC, and receive ADC. The AFE consumes 525 mW and provides better than 82-dB signal-to-noise-and-distortion ratio (SNDR) in both transmit and receive paths. It supports variable data rates from 64 kb/s up to 2.32 Mb/s, and enables an HDSL2 system to achieve better than 14 kft of noise-free reach (on 26-gauge wire) at 1.544 Mb/s. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A broadband high-voltage SLIC for a splitter- and transformerless combined ADSL-Lite/POTS linecard

    Page(s): 1976 - 1987
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (315 KB)  

    A monolithic broadband subscriber line interface circuit (B-SLIC) has been integrated in the smart power technology SPT170B, combining the functionality of an analog 150-V ringing SLIC with that of a line driver for ADSL-Lite data signals. Thus the B-SLIC is the key circuit for the realization of a very compact integrated voice data (IVD) central office linecard that neither needs analog filters ("POTS-splitter") nor transformers or relays. In spite of the fundamental voltage/frequency tradeoff, the B-SLIC is able to feed high dc or ring voltages to the line, while simultaneously acting as voice and data transceiver. Total harmonic distortion values are below -60 dB even for a high 25-V/sub pp//550-kHz sine wave signal into a 200 /spl Omega/ load; ADSL-signal-based multitone power ratio (MTPR) measurements also yield results better than 60 dB. Power dissipation in simultaneous voice and data operation is about 2.2 W. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan