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IEEE Design & Test of Computers

Issue 2 • April 1990

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Displaying Results 1 - 5 of 5
  • Integrating tester pin electronics

    Publication Year: 1990, Page(s):4 - 14
    Cited by:  Papers (4)
    Request permission for commercial reuse | PDF file iconPDF (845 KB)
    Freely Available from IEEE
  • Low-cost testing of high-density logic components

    Publication Year: 1990, Page(s):15 - 28
    Cited by:  Papers (22)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1129 KB)

    The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester's design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in eac... View full abstract»

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  • Built-in self-test of the Macrolan chip

    Publication Year: 1990, Page(s):29 - 40
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (910 KB)

    The implementation of self-test in the medium access controller chip for Macrolan, a fibre-optic, local area network, is described. The test style for 80% of the chip's combinational logic is quasiexhaustive testing. This approach, despite its apparent inefficiency in terms of the number of patterns used, gives considerable flexibility to the designer in arranging linear-feedback shift registers a... View full abstract»

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  • Implementing macro test in silicon compiler design

    Publication Year: 1990, Page(s):41 - 51
    Cited by:  Papers (16)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (870 KB)

    A testability strategy for a complex VLSI device that is implemented in the Piramid digital-signal-processor silicon compiler is presented. The macro test method proposed supports built-in self-test, scan test, restricted partial scan, and test-control logic at various levels in the design hierarchy. The strategy uses techniques such as a macro test plan, transfer information, and intermediate vec... View full abstract»

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  • Serial interfacing for embedded-memory testing

    Publication Year: 1990, Page(s):52 - 63
    Cited by:  Papers (120)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    A serial interfacing scheme in which several embedded memories share the built-in, self-test circuit is presented. For external testing, this approach requires only two serial pins for access to the data path. There is considerable savings in routing area, and fewer external pins are needed to test random-access memories with wide words, such as those in application-specific integrated circuits fo... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty