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IEEE Micro

Issue 2 • April 1990

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Displaying Results 1 - 7 of 7
  • Comments on 'A comparison of RISC architectures' by R.S. Piepho and W.S. Wu

    Publication Year: 1990
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (102 KB)

    For original article see ibid., vol.9, no.4, p.51-62, (Aug. 1989). The author points out that the relative addressing capability of a given architecture allows one to create position-independent code, that is, code (and data) that can be mapped anywhere in memory. The author notes that this capability is required to create shareable libraries, a feature that is available in the SunOS 4 and Unix Sy... View full abstract»

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  • The cache DRAM architecture: a DRAM with an on-chip cache memory

    Publication Year: 1990, Page(s):14 - 25
    Cited by:  Papers (25)  |  Patents (51)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1299 KB)

    A DRAM (dynamic RAM) with an on-chip cache, called the cache DRAM, has been proposed and fabricated. It is a hierarchical RAM containing a 1-Mb DRAM for the main memory and an 8-kb SRAM (static RAM) for cache memory. It uses a 1.2- mu m CMOS technology. Suitable for no-wait-state memory access in low-end workstations and personal computers, the chip also serves high-end systems as a secondary cach... View full abstract»

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  • Processing element design for a parallel computer

    Publication Year: 1990, Page(s):26 - 38
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB)

    A study has been made of how cost-effectiveness due to the improvement of VLSI technology can apply to a scientific computer system without performance loss. The result is a parallel computer, ADENA (Alternating Direction Edition Nexus Array), with a core consisting of four kinds of VLSI chips, two for processor elements (PES) and two for the interprocessor network (plus some memory chips). An ove... View full abstract»

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  • A 4-bit, 250-MIPS processor using Josephson technology

    Publication Year: 1990, Page(s):40 - 55
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1527 KB)

    An experimental 4-bit Josephson processor that demonstrates the possibility of a Josephson computer system with a gigahertz clock is presented. Constructed from 2066 gates on a 5-mm*5-mm die, it implements an eight-instruction set to enable the basic operations of digital signal processing. The basic structure and operating principles of the Josephson device are reviewed, and the design of and ope... View full abstract»

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  • Realizing the V80 and its system support functions

    Publication Year: 1990, Page(s):56 - 69
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1332 KB)

    An overview is given of the architecture of an overall design considerations for the 11-unit, 32-b V80 microprocessor, which includes two 1-kB cache memories and a branch prediction mechanism that is a new feature for microprocessors. The V80's pipeline processing and system support functions for multiprocessor and high-reliability systems are discussed. Using V80 support functions, multiprocessor... View full abstract»

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  • Microprocessor memory management units

    Publication Year: 1990, Page(s):70 - 85
    Cited by:  Papers (2)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2096 KB)

    This tutorial describes the current crop of commercial memory management units (MMUs) for 32-bit microprocessors. The discussion includes both complex- and reduced-instruction-set computers (CISCs and RISCs). The rationale, principles, and issues related to hardware support for memory management and virtual memory are reviewed. The design and features of high-end microprocessor MMUs are reviewed a... View full abstract»

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  • Micro Law-software patents

    Publication Year: 1990, Page(s):8 - 11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The concern that has been expressed in the computer industry about software patents is examined. Programmers fear that patents will be granted that monopolize basic concepts (such as pull-down windows or the use of menu bars) or algorithms that programmers need to write effective software. The Patent and Trademark Office seems to be willing to issue virtually any software patent presented to it, a... View full abstract»

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Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center