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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 10 • Date Oct 2000

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Displaying Results 1 - 13 of 13
  • Efficient implementation of a planar clock routing with the treatment of obstacles

    Publication Year: 2000, Page(s):1220 - 1225
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    This paper presents a set of techniques for developing a planar clock routing with the treatment of obstacles in high speed VLSI design. The planar clock routing framework has two key components. The first component employs a cutting-line embedding (CLE) routine algorithm to construct a planar clock tree topology. The routing constructed by CLE contains crossings over the obstacles in the presence... View full abstract»

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  • Automated synthesis of phase shifters for built-in self-test applications

    Publication Year: 2000, Page(s):1175 - 1188
    Cited by:  Papers (53)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    This paper presents novel systematic design techniques for the automated register transfer level synthesis of phase shifters-circuits used to remove effects of structural dependencies featured by pseudorandom test pattern generators driving parallel scan chains. Using a concept of linear feedback shift register (LFSR) duality this paper relates the logical states of LFSRs and circuits spacing thei... View full abstract»

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  • Symbolic timing analysis of asynchronous systems

    Publication Year: 2000, Page(s):1093 - 1104
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    We extend the time separations of events (TSE) timing analysis algorithm into the symbolic domain, that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the constraints on these symbolic variables which will ensure successful verifica... View full abstract»

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  • A new heuristic for rectilinear Steiner trees

    Publication Year: 2000, Page(s):1129 - 1139
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB)

    The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NP-hard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST heuristics is the Batched Iterated 1-Steiner (BI1S) heuristic of Kahng and Robins. In a recent develop... View full abstract»

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  • New approximation algorithms for routing with multiport terminals

    Publication Year: 2000, Page(s):1118 - 1128
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Previous literature on very large scale integration routing and wiring estimation typically assumes a one-to-one correspondence between terminals and ports. In practice, however, each “terminal” consists of a large collection of electrically equivalent ports, a fact that is not accounted for in layout steps such as wiring estimation. In this paper, we address the general problem of min... View full abstract»

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  • Congestion minimization during placement

    Publication Year: 2000, Page(s):1140 - 1148
    Cited by:  Papers (29)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is the least understood, however, it models routability most accurately. In this paper, we study the congestion minimization problem during placement. First, we show that a global placement with minimum wirelength has minimum total congestion. We show that minimizing wirelength may (and in ... View full abstract»

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  • Specification-driven test generation for analog circuits

    Publication Year: 2000, Page(s):1189 - 1201
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    In this paper, a new methodology for generating transient tests to detect faults in analog circuits is presented. Relationship between circuit functionalities and physical failures is exploited to derive these tests. These fast transient tests can be used for implicitly verifying the circuit specifications. A fast fault simulation algorithm for linear analog circuits based on state-space represent... View full abstract»

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  • Implicit enumeration of strongly connected components and an application to formal verification

    Publication Year: 2000, Page(s):1225 - 1230
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    This paper first presents a binary decision diagram-based implicit algorithm to compute all maximal strongly connected components (SCCs) of directed graphs. The algorithm iteratively applies reachability analysis and sequentially identifies SCCs. Experimental results suggest that the algorithm dramatically outperforms the only existing implicit method which must compute the transitive closure of t... View full abstract»

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  • Test scheduling for core-based systems using mixed-integer linear programming

    Publication Year: 2000, Page(s):1163 - 1174
    Cited by:  Papers (110)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (936 KB)

    We present optimal solutions to the test scheduling problem for core-based systems. Given a set of tasks (test sets for the cores), a set of test resources (e.g., test buses, BIST hardware) and a test access architecture, we determine start times for the tasks such that the total test application time is minimized. We show that the test scheduling decision problem is equivalent to the m-processor ... View full abstract»

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  • A temperature-aware simulation environment for reliable ULSI chip design

    Publication Year: 2000, Page(s):1211 - 1220
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    In this paper, we present a temperature-aware simulation environment, iTAS, which has been developed for the design of thermally reliable ultra-large scale integrated (ULSI) chips. This environment provides advisory information from the early chip design phase to the post-layout analysis phase. Several important applications, including temperature-sensitive timing analysis, efficient on-chip hot-s... View full abstract»

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  • Automatic checking of aggregation abstractions through state enumeration

    Publication Year: 2000, Page(s):1202 - 1210
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    Aggregation abstraction is a way of defining a desired correspondence between an implementation of a transaction-oriented protocol and a much simpler idealized version of the same protocol. This relationship can be formally verified to prove the correctness of the implementation. We present a technique for checking aggregation abstractions automatically using a finite-state enumerator. The abstrac... View full abstract»

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  • Integrating variable-latency components into high-level synthesis

    Publication Year: 2000, Page(s):1105 - 1117
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Components used as building blocks (e.g., functional units) in conventional HLS techniques are assumed to have fixed latency values. Variable-latency units exhibit the property that the number of cycles taken to compute their outputs varies depending on the input values. While variable-latency units offer potential for performance improvement, we demonstrate that realization of this potential requ... View full abstract»

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  • Sequential synthesis using S1S

    Publication Year: 2000, Page(s):1149 - 1162
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we derive a logical expression which yields a single finite state automaton characterizing the set of impleme... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu