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IEEE Transactions on Computers

Issue 8 • Aug 2000

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Displaying Results 1 - 7 of 7
  • On-the-fly algorithms and sequential machines

    Publication Year: 2000, Page(s):859 - 863
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    It is shown that a function is computable by an on-the-fly algorithm processing data in the most significant digit first fashion with a finite number of registers if and only if it is computable by a right subsequential finite state machine processing deterministically data in the least significant digit first fashion. Some applications to complex radix number systems are given View full abstract»

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  • V-NET: A versatile network architecture for flexible delay guarantees in real-time networks

    Publication Year: 2000, Page(s):841 - 858
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1100 KB)

    This paper proposes a Versatile Network Architecture (V-NET) to support flexible delay guarantees for applications in real-time networks. Applications communicate over the V-NET by using end-to-end network connections which support real-time and reliability characteristics tailored to meet the application's specified requirements. V-NET differs from other proposed architectures in that, in additio... View full abstract»

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  • Design and evaluation of a switch cache architecture for CC-NUMA multiprocessors

    Publication Year: 2000, Page(s):779 - 797
    Cited by:  Papers (5)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1536 KB)

    Cache coherent nonuniform memory access (CC-NUMA) multiprocessors provide a scalable design for shared memory. But, they continue to suffer from large remote memory access latencies due to comparatively slow memory technology and large data transfer latencies in the interconnection network. In this paper, we propose a novel hardware caching technique, called switch cache, to improve the remote mem... View full abstract»

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  • Computing orthogonal drawings with the minimum number of bends

    Publication Year: 2000, Page(s):826 - 840
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    We describe a branch-and-bound algorithm for computing an orthogonal grid drawing with the minimum number of bends of a biconnected planar graph. Such an algorithm is based on an efficient enumeration schema of the embeddings of a planar graph and on several new methods for computing lower bounds of the number of bends. We experiment with such algorithm on a large test suite and compare the result... View full abstract»

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  • On optimal replacement of nonuniform cache objects

    Publication Year: 2000, Page(s):769 - 778
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    This paper studies a generalized version of the well-known page replacement problem. It assumes that page sizes and page fault penalties are nonuniform. This problem arises in distributed information systems, in particular the World Wide Web. It is shown that finding an optimal solution of this problem is an NP-complete problem. A dynamic programming algorithm that finds an optimal solution is pre... View full abstract»

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  • Location consistency-a new memory model and cache consistency protocol

    Publication Year: 2000, Page(s):798 - 813
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    Existing memory models and cache consistency protocols assume the memory coherence property which requires that all processors observe the same ordering of write operations to the same location. In this paper, we address the problem of defining a memory model that does not rely on the memory coherence assumption and also the problem of designing a cache consistency protocol based on such a memory ... View full abstract»

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  • Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility

    Publication Year: 2000, Page(s):814 - 825
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1244 KB)

    The object-code compatibility problem in VLIW architectures stems from their statically scheduled nature. Dynamic rescheduling (DR) is a technique to solve the compatibility problem in VLIWs. DR reschedules program code pages at first-time page faults, i.e., when the code pages are accessed for the first time during execution. Treating a page of code as the unit of rescheduling makes it susceptibl... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org