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Solid-State Circuits, IEEE Journal of

Issue 9 • Date Sept. 2000

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Displaying Results 1 - 18 of 18
  • Introduction to the 21st annual IEEE GaAs IC symposium

    Publication Year: 2000 , Page(s): 1258 - 1259
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    Freely Available from IEEE
  • High-gain transimpedance amplifier in InP-based HBT technology for the receiver in 40-Gb/s optical-fiber TDM links

    Publication Year: 2000 , Page(s): 1260 - 1265
    Cited by:  Papers (15)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (609 KB)  

    A monolithic integrated transimpedance amplifier for the receiver in a 40-Gb/s optical-fiber TDM system has been fabricated in an InP-based HBT technology. Despite its high gain (transimpedance of 2 k/spl Omega/ in the limiting mode, 10 k/spl Omega/ in the linear mode) the complete amplifier was realized on a single chip. Clear output eye diagrams were measured up to 43 Gb/s under realistic driving conditions. The voltage swing of 0.6 V/sub pp/ at the differential 50 /spl Omega/ output does not change within the demanded input dynamic range of 6 dB. At the upper input current level even 48 Gb/s were achieved. The power consumption is approximately 600 mW at a single supply voltage of -5.5 V. View full abstract»

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  • A 3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology

    Publication Year: 2000 , Page(s): 1266 - 1270
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (143 KB)  

    We present a pseudorandom bit sequence (PRBS) generator that outputs a 2/sup 7/-1 bit pattern at rates up to 21 Gb/s. The circuit is implemented in a 40-GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) standard production process, operates from a single 3.3-V power supply, and consumes 1.1 W of power. We discuss variations of PRBS architecture and digital circuit topologies which exploit unique characteristics of AlGaAs/GaAs HBT devices. The work demonstrates the feasibility of using AlGaAs/GaAs HBT technology with low-voltage/low-power design techniques in complex high-speed circuits. View full abstract»

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  • 3-V MSM-TIA for Gigabit Ethernet

    Publication Year: 2000 , Page(s): 1271 - 1275
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (298 KB)  

    The paper describes a 3-V monolithically integrated metal-semiconductor-metal photodetector (MSM-PD) and transimpedance amplifier (TIA) chip that is fully compliant with the Gigabit Ethernet receiver specification for the short-reach application (IEEE 802.3z 1000BASE-SX). Key typical performance specifications are -22 dBm sensitivity, 1200 MHz 3-dB bandwidth, 1300-V/W differential responsivity, and 120-mW power dissipation at 3 V. The chip is fabricated in a production 0.5-/spl mu/m gate length GaAs MESFET technology and is packaged in a TO-46 header with a flat window and a ball-lens cap option. View full abstract»

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  • Application of enhancement mode FET technology for wireless subscriber transmit/receive circuits

    Publication Year: 2000 , Page(s): 1276 - 1284
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (374 KB)  

    Single-supply power amplifiers have become the new paradigm in portable phone handsets due to the recent availability of heterojunction bipolar transistor (HBT) and pseudo enhancement mode PHEMT technology. We have developed a true enhancement mode heterostructure insulated-gate FET device (HIGFET) which is suitable for use in both saturated and linear power amplifiers. A three-stage power amplifier designed for 1900-MHz NADC application delivered +30-dBm output power and 41.7% power-added efficiency with an adjacent channel power of -29.8 dBc and alternate adjacent channel power of -48.4 dBc. In addition to this, we have demonstrated excellent noise figure and linearity performance for small-signal applications. At 900 MHz and bias conditions V/sub DS/=1.0 V and I/sub DSQ/=1 mA, a single-stage amplifier achieved a noise figure of 1.17 dB with an associated gain of 18.5 dB. These results make the technology an ideal candidate for application in both transmitter and receiver circuits. View full abstract»

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  • Broadband GaAs MESFET and GaN HEMT resistive feedback power amplifiers

    Publication Year: 2000 , Page(s): 1285 - 1292
    Cited by:  Papers (16)
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    We report 0.2 to 6-GHz MMIC power amplifiers with 12-dB gain, over 23-dBm output power, and more than 25% power-added efficiency (PAE) in a GaAs MESFET technology offering 18 GHz f/sub /spl tau// and 12-V breakdown. These circuits have gain-bandwidth products of /spl sim/1.3/spl middot/f/sub /spl tau// and are more efficient than distributed power amplifiers. A first demonstration of similar circuits in GaN/AlGaN HEMT technology yielded 11-dB gain, 0.2 to 7.5-GHz bandwidth amplifiers with over 31.5-dBm output power and up to 15% PAE. With improved devices and models we expect significantly higher power from the GaN HEMT circuits. View full abstract»

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  • A CW 4-W Ka-band power amplifier utilizing MMIC multichip technology

    Publication Year: 2000 , Page(s): 1293 - 1297
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB)  

    This paper describes a 28-GHz power amplifier with 4.5-W output power under CW operation. The amplifier utilizes four fully matched MMICs, in which 0.35-/spl mu/m-long gate GaAs-based heterojunction FETs are employed. The developed power amplifier also provides a continuous-wave (CW) output power of 3 W over the bandwidth of 2 GHz at Ka-band. View full abstract»

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  • Design and fabrication of a wideband 56- to 63-GHz monolithic power amplifier with very high power-added efficiency

    Publication Year: 2000 , Page(s): 1298 - 1306
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (478 KB)  

    This paper describes the design, fabrication, and measurement of a wideband 60 GHz monolithic microwave integrated circuit (MMIC) power amplifier that has demonstrated via on-wafer continuous wave (CW) measurement a record 43% power-added efficiency (PAE) at an associated output power of 224 mW and 7.5 dB of power gain. At a higher drain bias of 3.5 V, the CW output power increased to 250 mW with 38.5% PAE. Additional performance improvement is expected when the MMICs are tested on-carrier with proper heat sinking. These state-of-the-art first-pass design results can be attributed to: 1) the use of a fully selective gate recess etch 0.12-/spl mu/m InP HEMT process fabricated on 2-mm-thick 3-in diameter InP substrates with slot via holes; 2) a design based on a novel on-wafer load-pull measurement technique; and 3) an accurate large-signal nonlinear model for InP HEMTs. In order to reach the low cost required for mass production, the same MMIC design was fabricated on an InP metamorphic HEMT (MHEMT) process. The MHEMT version of the MMIC demonstrated 41.5% PAE, with an associated output power of 183 mW (305 mW/mm) and 6.9 dB of power at 60 GHz when measured CW on-wafer. These InP HEMT and MHEMT results are, to our knowledge, the highest PAE and power bandwidth ever reported at V-band. View full abstract»

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  • Millimeter-wave low-noise and high-power metamorphic HEMT amplifiers and devices on GaAs substrates

    Publication Year: 2000 , Page(s): 1307 - 1311
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (186 KB)  

    This paper reports on state of-the-art HEMT devices and circuit results utilizing 32% and 60% indium content InGaAs channel metamorphic technology on GaAs substrates. The 60% In metamorphic HEMT (MHEMT) has achieved an excellent 0.61-dB minimum noise figure with 11.8 dB of associated gain at 26 GHz. Using this MHEMT technology, two and three-stage Ka-band low-noise amplifiers (LNAs) have demonstrated <1.4-dB noise figure with 16 dB of gain and <1.7 with 26 dB of gain, respectively. The 32% In MHEMT device has overcome the <3.5-V drain bias limitation of other MHEMT power devices, showing a power density of 650 mW/mm at 35 GHz, with V/sub ds/=6 V. View full abstract»

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  • 94/47-GHz regenerative frequency divider MMIC with low conversion loss

    Publication Year: 2000 , Page(s): 1312 - 1317
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (238 KB)  

    A coplanar regenerative frequency divider monolithic microwave integrated circuit (MMIC) based on 0.15-/spl mu/m pHEMTs on GaAs for 94/47-GHz frequency conversion has been developed, achieving a bandwidth of 23% for stable division. A very low conversion loss of 2.5 dB was obtained with an input level of -2 dBm and a dc power consumption of 8 mW, without using additional buffer amplifiers. The frequency of operation can be tuned by a varactor diode in the feedback network over a 2.5-GHz range to compensate for technology variations. Various methods for the simulation of stable and unstable operation and bandwidth and conversion performance are presented, using accurate modeling of the active and passive components. View full abstract»

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  • Introduction to the 1999 Bipolar/BiCMOS Circuits and Technology Meeting

    Publication Year: 2000 , Page(s): 1318 - 1319
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    Freely Available from IEEE
  • A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC

    Publication Year: 2000 , Page(s): 1320 - 1328
    Cited by:  Papers (44)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (487 KB)  

    This paper describes a single-chip implementation of a low-voltage image-reject downconverter for a 5.1-5.8-GHz radio receiver. It consists of a low-noise preamplifier (LNA) that is simultaneously noise and power matched to the RF source, and dual doubly balanced mixers coupled to the LNA by a monolithic trifilar transformer. The image-reject architecture eliminates an RF filter, thereby simplifying packaging requirements. The downconverter realizes over 36 dB of image rejection while dissipating 24 mW from a 0.9 V supply, or 18.5 mW at 1.8 V. Conversion gain is 14 dB, IIP3=-5.5 dBm, and noise figure is 6.8 dB (single sideband 50 /spl Omega/) when operating from a 0.9 V supply. View full abstract»

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  • A wide-bandwidth Si/SiGe HBT direct conversion sub-harmonic mixer/downconverter

    Publication Year: 2000 , Page(s): 1329 - 1337
    Cited by:  Papers (67)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (319 KB)  

    A wideband sub-harmonic mixer/direct-conversion downconverter is implemented in a Si/SiGe HBT technology, with improved rejection of the local oscillator (LO), high input intercept point, and low current requirements. The circuit utilizes a combination of phase shifters operating at 45/spl deg/ and 90/spl deg/ to achieve better than 33-dB input-referred rejection of the LO. The measured third-order input intercept point (IIP3) was approximately -3 dBm and the second-order input intercept point (IIP2) was roughly 35 dBm, with a measured double sideband (DSB) noise figure of 7.8 dB. A comparison was made between devices of differing germanium concentration in the base, and the devices with higher Ge content exhibited improved noise figure and gain. Each mixer required approximately 2.8 mA from a 3.3 V supply. View full abstract»

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  • A 3-V monolithic SiGe HBT power amplifier for dual-mode (CDMA/AMPS) cellular handset applications

    Publication Year: 2000 , Page(s): 1338 - 1344
    Cited by:  Papers (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB)  

    A dual-mode (CDMA/AMPS) power amplifier has been successfully implemented by using a monolithic SiGe/Si heterojunction bipolar transistor (HBT) foundry process for cellular handset (824-849 MHz) applications. The designed two-stage power amplifier satisfies both CDMA and AMPS requirements in output power, linearity, and efficiency. At V/sub cc/=3 V,the power amplifier shows an excellent linearity (first ACPR<-44.1 dBc and second ACPR<-57.1 dBc) up to 28 dBm of output power for CDMA applications. Under the same bias condition, the power amplifier also meets AMPS handset requirements in output power (up to 31 dBm) and linearity (with second and third harmonic to fundamental ratios lower than -37 dBc and -55 dBc, respectively). At the maximum output power level, the worst power-added efficiencies (PAEs) are measured to be 36% for CDMA and 49% for AMPS operations. The power amplifier also tolerates severe output mismatch (VSWR>12:1) up to V/sub cc/=4 V, with spurs measured to be <-22 dBc in CDMA outputs at two specific tuning angles, but with no spur in AMPS outputs at any tuning angle. View full abstract»

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  • A current-folded up-conversion mixer and VCO with center-tapped inductor in a SiGe-HBT technology for 5-GHz wireless LAN applications

    Publication Year: 2000 , Page(s): 1345 - 1352
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (505 KB)  

    This paper describes a 5.8-GHz up-conversion mixer core based on a current-folded architecture and a 5-GHz differential emitter-coupled voltage-controlled oscillator (VCO) utilizing a center-tapped inductor and a substrate shield. Both circuits are fabricated in a 0.8-/spl mu/m 45-GHz f/sub T/ SiGe heterojunction bipolar transistor (HBT) technology. The supply voltage range is between -2.3 V and -3.3 V to meet the requirements of mobile circuits. Special care has been taken with the inductor model. A distributed modeling approach was used to generate an inductor model from a geometrical description. This type of model also has the advantage that it can simulate RF effects in both time and frequency domain. View full abstract»

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  • SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application

    Publication Year: 2000 , Page(s): 1353 - 1359
    Cited by:  Papers (30)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (506 KB)  

    An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV/sub pp/ at a bit error rate (BER)=10/sup -9/. The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply. View full abstract»

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  • The effect of varactor nonlinearity on the phase noise of completely integrated VCOs

    Publication Year: 2000 , Page(s): 1360 - 1367
    Cited by:  Papers (64)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (274 KB)  

    This work discusses variations in phase noise over the tuning range of a completely integrated 1.9-GHz differential voltage-controlled oscillator (VCO) fabricated in a 0.5-/spl mu/m bipolar process with 25-GHz f/sub t/. The design had a phase noise of -103 dBc/Hz at 100 kHz offset at the top of the tuning range, but the noise performance degraded to -96 dBc/Hz at 100 kHz at the bottom of the tuning range. It was determined that nonlinearities of the on-chip varactors, which led to excessively high VCO gain at the bottom of the tuning range, were primarily responsible for this degradation in performance. The VCO has a power output of -5 dBm per side. Calculations predict phase noise with only a small error and provide design insight for minimizing this effect. The oscillator core drew 6.4 mA and the output buffer circuitry drew 6 mA, both from a 3.3-V supply. View full abstract»

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  • Monolithic transformers for silicon RF IC design

    Publication Year: 2000 , Page(s): 1368 - 1382
    Cited by:  Papers (333)  |  Patents (49)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    A comprehensive review of the electrical performance of passive transformers fabricated in silicon IC technology is presented. Two types of transformer construction are considered in detail, and the characteristics of two-port (1:1 and 1:n turns ratio) and multiport transformers (i.e., baluns) are presented from both computer simulation and experimental measurements. The effects of parasitics and imperfect coupling between transformer windings are outlined from the circuit point of view. Resonant tuning is shown to reduce the losses between input and output at the expense of operating bandwidth. A procedure for estimating the size of a monolithic transformer to meet a given specification is outlined, and circuit examples are used to illustrate the applications of the monolithic transformer in RF ICs. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan