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IEEE Transactions on Computers

Issue 6 • Date June 2000

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Displaying Results 1 - 9 of 9
  • Guest editors' introduction

    Publication Year: 2000, Page(s):529 - 531
    Request permission for commercial reuse | PDF file iconPDF (213 KB)
    Freely Available from IEEE
  • Continuous learning automata solutions to the capacity assignment problem

    Publication Year: 2000, Page(s):608 - 620
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The Capacity Assignment (CA) problem focuses on finding the best possible set of capacities for the links that satisfies the traffic requirements in a prioritized network while minimizing the cost. Most approaches consider a single class of packets flowing through the network, but, in reality, different classes of packets with different packet lengths and priorities are transmitted over the networ... View full abstract»

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  • Procedures for static compaction of test sequences for synchronous sequential circuits

    Publication Year: 2000, Page(s):596 - 607
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    We propose three static compaction techniques for test sequences of synchronous sequential circuits. We apply the proposed techniques to test sequences generated for benchmark circuits by various test generation procedures. The results show that the test sequences generated by all the test generation procedures considered can be significantly compacted. The compacted sequences thus have shorter te... View full abstract»

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  • An efficient reconfiguration algorithm for degradable VLSI/WSI arrays

    Publication Year: 2000, Page(s):553 - 559
    Cited by:  Papers (42)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    This paper considers the problem of reconfiguring two-dimensional degradable VLSI/WSI arrays under the constraint of row and column rerouting. The goal of the reconfiguration problem is to derive a fault-free subarray T from the defective host array such that the dimensions of T are larger than some specified minimum. This problem has been shown to be NP-complete under various switching and routin... View full abstract»

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  • Incorporating yield enhancement into the floorplanning process

    Publication Year: 2000, Page(s):532 - 541
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    The traditional goals of the floorplanning process for a new integrated circuit have been minimizing the total chip area and reducing the routing cost, i.e., the total length of the interconnecting wires. Recently, it has been shown that, for certain types of chips, the floorplan can affect the yield of the chip as well. Consequently, it becomes desirable to consider the expected yield, in additio... View full abstract»

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  • Fault-tolerant Newton-Raphson and Goldschmidt dividers using time shared TMR

    Publication Year: 2000, Page(s):588 - 595
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Iterative division algorithms based on multiplication are popular because they are fast and may utilize an already existing hardware multiplier. Two popular methods based on multiplication are Newton-Raphson and Goldschmidt's algorithm. To achieve concurrent error correction, Time Shared Triple Modular Redundancy (TSTMR) may be applied to both kinds of dividers. The hardware multiplier is divided ... View full abstract»

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  • Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines

    Publication Year: 2000, Page(s):560 - 574
    Cited by:  Papers (45)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    We present a self-checking detection and diagnosis scheme for transient, delay, and crosstalk faults affecting bus lines of synchronous systems. Faults that are likely to result in the connected logic sampling incorrect bus data are on-line detected. The position of the affected line(s) within the considered bus is identified and properly encoded. The proposed scheme is self-checking with respect ... View full abstract»

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  • Fault-tolerant processor arrays based on the 1½-track switches with flexible spare distributions

    Publication Year: 2000, Page(s):542 - 552
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A mesh-connected processor array consists of many similar processing elements (PEs) which can be executed in both parallel and pipeline processing. For the implementation of an array of large numbers of processors, some fault-tolerant issues are necessary to enhance the (fabrication-time) yield and the (run-time) reliability. In this paper, we propose a fault-tolerant reconfigurable processor arra... View full abstract»

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  • On the adaptation of Viterbi algorithm for diagnosis of multiple bridging faults

    Publication Year: 2000, Page(s):575 - 587
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB)

    This paper proposes a very efficient method to diagnosis multiple bridging faults. This method is based on differential or Delta IDDQ probabilistic signatures, as well as on the Viterbi algorithm, mainly used in telecommunications systems for error correction. The proposed method can be seen as a significant improvement over an existing one based on maximum likelihood estimation. The u... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org