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Electron Devices, IEEE Transactions on

Issue 9 • Date Sep 2000

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Displaying Results 1 - 15 of 15
  • Effects of NH3-plasma nitridation on the electrical characterizations of low-k hydrogen silsesquioxane with copper interconnects

    Page(s): 1733 - 1739
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    The interaction between copper interconnects and low-k hydrogen silsesquioxane (HSQ) film was investigated using a Cu/HSQ/Si metal insulation semiconductor capacitor and NH3 plasma post-treatment. Owing to serious diffusion of copper atoms in HSQ film, degradations of the dielectric properties are significant with the increase of thermal stress. The leakage current behavior in high field conduction is well explained by the Poole-Frenkel (P-F) mechanism. By applying NH3-plasma treatment to the HSQ film, however, the leakage current is decreased and P-F conduction can be significantly suppressed. In addition, the phenomenon of serious Cu penetration is not observed by means of electrical characteristic measurements and secondary ion mass spectroscopy (SIMS) analysis even in the absence of diffusion barrier layers. This indicates the copper diffusion in low-k HSQ film can he effectively blocked by NH3 plasma post-treatment View full abstract»

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  • GaAs quantum wire lasers grown on v-grooved substrates isolated by self-aligned ion implantation

    Page(s): 1769 - 1772
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    Multiple vertically stacked GaAs/AlxGa1-xAs quantum wires laser diodes have been fabricated via MOVPE on v-grooved GaAs substrates. The devices are electrically isolated by oxygen ion implantation, utilizing the nonplanarity of the device. The process is self-aligning and requires no masking, yielding significant simplification in the device fabrication. Optimum implant conditions are determined. A quantum internal efficiency of 65.8% is measured for the optimum implanted devices, which exhibit a 5.5 mA threshold current View full abstract»

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  • Current-voltage characteristics of high current density silicon Esaki diodes grown by molecular beam epitaxy and the influence of thermal annealing

    Page(s): 1707 - 1714
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    We present the characteristics of uniformly doped silicon Esaki tunnel diodes grown by low temperature molecular beam epitaxy (Tgrowth=275°C) using in situ boron and phosphorus doping. The effects of ex situ thermal annealing are presented for temperatures between 640 and 800°C. A maximum peak to valley current ratio (PVCR) of 1.47 was obtained at the optimum annealing temperature of 680°C for 1 min. Peak and valley (excess) currents decreased more than two orders of magnitude as annealing temperatures and times were increased with rates empirically determined to have thermal activation energies of 2.2 and 2.4 eV respectively. The decrease in current density is attributed to widening of the tunneling barrier due to the diffusion of phosphorus and boron. A peak current density of 47 kA/cm2 (PVCR=1.3) was achieved and is the highest reported current density for a Si-based Esaki diode (grown by either epitaxy or by alloying). The temperature dependence of the current voltage characteristics of a Si Esaki diode in the range from 4.2 to 325 K indicated that both the peak current and the excess current are dominated by quantum mechanical tunneling rather than by recombination. The temperature dependence of the peak and valley currents is due to the band gap dependence of the tunneling probability View full abstract»

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  • Validity and applicability of triangular potential well approximation in modeling of MOS structure inversion and accumulation layer

    Page(s): 1764 - 1767
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    Two methods are presented to calculate the carrier distribution in MOS inversion and accumulation layer by self-consistent solution of Schrodinger and Poisson equations. One is the fully numerical solution of Schrodinger equation by finite difference method and the other is the analytical solution of Schrodinger equation under triangular potential well approximation. The effective electric field used in the analytical solution is properly determined. Results show that both carrier sheet density and surface potential in inversion layer and accumulation layer can be determined by analytical solution under triangular potential well approximation with sufficiently high accuracy. However, the carrier distribution profile and centroid of mobile charge layer, as well as the behavior at the flat-band region, have a large deviation from the numerical results View full abstract»

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  • Dynamic range improvement by narrow-channel effect suppression and smear reduction technologies in small pixel IT-CCD image sensors

    Page(s): 1700 - 1706
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    Technologies for narrow-channel effect suppression in photodiodes (PDs) and vertical CCDs (V-CCDs) and for smear reduction in PDs have been developed in order to improve dynamic range in small pixel interline-transfer CCD (IT-CCD) image sensors. The new technologies have been applied to a progressive-scan IT-CCD image sensor with 5 μm square pixels and have (1) increased the charge handling capability of its V-CCDs to 4500 electrons/V; (2) improved its smear value to -95 dB; and (3) increased the saturation charge of its PDs to 2.3×104 electrons View full abstract»

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  • Improved correlation measurements using voltage and transimpedance amplifiers in low-frequency noise characterization of bipolar transistors

    Page(s): 1772 - 1773
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    A method is presented to improve accuracy in low-frequency noise characterization of bipolar transistors by using both a voltage amplifier and transimpedance amplifiers View full abstract»

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  • Analysis of fast electrothermal dynamics in power BJT

    Page(s): 1758 - 1763
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    It is well known that the self heating phenomenon in power bipolar devices strongly influences the electrical behavior. Heating phenomenon is a dynamic process ruled by different time constants. While the thermal dynamics associated to external heat exchange is an order of magnitude slower than the electrical one, the thermal dynamics occurring at the silicon level near the active junction is relatively faster and can interact with the electrical one. In this paper, it is proved that such a fast thermal dynamics is responsible for unstable oscillating electrical transients that can be detected in power bipolar transistors. An electrothermal resonance phenomenon Is theoretically and experimentally verified on a commercial power BJT. It is explained how such a phenomenon ran be operatively employed to extract the parameters of the fast thermal dynamics, difficult to measure with conventional procedures View full abstract»

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  • A new test structure for extracting extrinsic parameters in double-polysilicon bipolar transistors

    Page(s): 1767 - 1769
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    A new test structure for parameter extraction is presented and implemented in a double-polysilicon bipolar junction transistor (BJT) process. The test structure is basically a real BJT, but without the intrinsic base. The test structure allows extraction of the base, collector and emitter impedances, and the extrinsic base-collector capacitance View full abstract»

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  • AC characteristics of Cr/p+a-Si:H/V analog switching devices

    Page(s): 1751 - 1757
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    Experimental results on the ac characteristics of electro-formed Cr/p+ hydrogenated amorphous silicon (a-Si:H)/V thin film memory devices are presented. The impedance spectrum of the memory switching device has been measured over a wide frequency range from 1 Hz-32 MHz while keeping the ac voltage amplitude below 0.02 V. Simulation of the measured impedance spectrum using an equivalent circuit indicates that the capacitance associated with a conducting filament tends to increase as the memory resistance decreases. This is explained on the basis of an activated tunnelling mechanism. Charge transport is dominated by electron tunnelling via metallic particles in the filament, and hence small changes in interparticle spacing influences the tunnelling process considerately, leading to changes in both memory resistance and effective dielectric constant View full abstract»

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  • EL characteristics of a TFEL/TFT stacked structure display device driven by a HV-Si·TFT circuit

    Page(s): 1694 - 1699
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    TFEL/TFT stacked structure display devices were fabricated onto a quartz substrate. By using a HV-TFT circuit as the basis of a TFEL/TFT device, an EL device on the TFT circuit can be switched at a sufficiently low signal line voltage of Vs=2-3 V. The maximum brightness of the TFEL/TFT device is 230 cd/m2 and the ON/OFF brightness ratio is more than 90 between Vs=0 and Vs=4 V at a Vapp frequency of 5 kHz and a voltage of 50. Evaluation of the dynamic behavior of TFT circuits using multichannel HV-Si·TFT's showed that the rise time of the fundamental TFT circuit at the EL driving point of the circuit was about 20 μs and that the hold time of the circuit was about 70 mS. The rise time and the fall time of the luminescence were each about 20 μs. The memory characteristics of the TFEL/TFT device showed that the hold time of the luminescence was about 40 mS. These dynamic characteristics of the TFEL/TFT stacked structure device satisfy the conditions required for a flat panel display View full abstract»

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  • Two formulations of semiconductor transport equations based on spherical harmonic expansion of the Boltzmann transport equation

    Page(s): 1726 - 1732
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    Two different formulations of semiconductor transport models based on the spherical harmonic expansion of the Boltzmann transport equation are presented. In the one-dimensional (1-D) case, macroscopic transport coefficients are defined through Legendre components of the distribution function. Although either formulation is permissible, the modeling of transport coefficients in one of the formulations is more tractable than the other. The validity of the Einstein and other relations are also examined. The two different transport formulations are then applied to the hydrodynamic simulation of an n+-n-n+ structure and results are compared with the Monte Carlo simulation data View full abstract»

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  • Noise associated with interdigitated gate structures in RF submicron MOSFETs

    Page(s): 1745 - 1750
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    CMOS technologies have gained considerable attention and have raised expectations for employment in RF transceivers. The shrinkage of the MOSFET device dimensions along with the relatively wide gate electrode devices needed to accommodate RF applications lead to reconsideration of the noise properties of submicron MOSFETs. In this paper, we present the noise properties associated with interconnect resistors of an interdigitated structure and the resulting noise source (strong function of the number of fingers) is evaluated against the other noise sources present in the device such as channel thermal noise, induced gate noise, and resistive gate voltage noise. Short channel effects have been taken into account for the evaluation of these noise sources and two-port analysis performed in order to calculate minimum noise figure and optimum input resistance for noise matching View full abstract»

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  • Dead space effect on the wavelength dependence of gain and noise in avalanche photodiodes

    Page(s): 1685 - 1693
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    We extend the dead space model proposed by Hayat et al. in order to determine the wavelength-dependent multiplication mean gain ⟨G(λ)⟩ and excess noise factor F(λ) in the case of mixed electron and hole injection, as it is the case when photons are absorbed within the multiplication region. We compare the predictions of the model with measurements performed on a silicon ultraviolet-selective avalanche photodiode with submicron thick multiplication region. We show that the multiplication gain is constant in the visible and near-infrared part of the spectrum, and increases in the UV range by a factor of 1.8. Furthermore, the excess noise factor is minimal for UV radiation and increases rapidly for longer wavelengths. It appears that the extended dead space model is very adequate at predicting the gain and noise measurement results. In order to unambiguously determine the effect of the dead space, we compare the predictions of our model with those of McIntyre's local noise model. The latter qualitatively describes the wavelength dependence of the gain, but greatly overestimates the excess noise factor View full abstract»

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  • Design, fabrication, and analysis of SiGeC heterojunction PMOSFETs

    Page(s): 1715 - 1725
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    We present the evaluation of the strain-stabilizing capabilities of C in the Si1-xGex system. To demonstrate these effects, we have designed Si1-x-yGexCy heterojunction PMOSFET devices over a range of Ge concentrations, with thicknesses that would typically result in related or metastable films under normal processing conditions. The dc characteristics of Si1-x-yGexCy, SiCe, and Si PMOSFETs (L=10 μm) were evaluated at room temperature and at 77 K. In general, the saturation mobility in Si1-x-yGexCy devices is higher than that of Si1-xGex and Si devices at low gate bias and room temperature. This enhancement is attributed to the strain stabilization effect of C. With proper optimization of Ge and C concentrations, it is possible to fabricate devices with significant improvements in drive current under normal operating conditions (0-3 V, 300 K). This application of Si1-x-y GexCy in PMOSFETs demonstrates the potential benefits of using of C in the Column IV heterostructure system View full abstract»

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  • Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations

    Page(s): 1740 - 1744
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    This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology