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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 8 • Date Aug 2000

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Displaying Results 1 - 17 of 17
  • Efficient architectures for time-interleaved oversampling delta-sigma converters

    Page(s): 802 - 810
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    A design methodology utilizing the concept of time-interleaved oversampling delta-sigma conversion is developed and explored to obtain efficient hardware architectures. In this approach, the time-domain internal node expressions of a standard modulator are rearranged according to the desired channel count to produce a modular structure with reduced hardware requirements. It is shown that the proposed approach results in an architecture which is functionally equivalent to that of the conventional method based on the block-digital filtering concept, but with a reduced hardware complexity. The theoretical results are also verified by means of behavioral simulations View full abstract»

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  • Optimal subband coders of quantized multidimensional signals

    Page(s): 757 - 770
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    A new general method is presented for the analysis of the effects of quantization and transmission noise in subband filter-bank multidimensional signal and image coders. Using general statistical noise characterization, the filter banks are obtained, which are optimal in the sense of minimizing the variance of the difference of the reconstructed signal from the original. It is shown that these are not identical to those achieving perfect reconstruction in lossless coding. A general method is described for the optimal selection of the synthesis filters if the analysis filters and quantizers are given. Assuming the use of these optimal synthesis filters, a method is then developed for the determination of the optimal analysis filters and the optimal bit-allocation to the subbands. The effects of quantization on perfect reconstruction filter-banks are analyzed next, and an explicit expression is determined for the quantizer noise-to-signal ratio for such banks. Given arbitrary quantizers, the analysis filters which are optimal in the sense of minimizing the output noise power are obtained. Finally, the jointly optimal selection is determined for the analysis filters and the bit allocations of the subbands. It is seen that this selection is identical to that determined for the theoretically optimal filter-banks View full abstract»

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  • Multivalued characteristics in electronic circuits: a unifying approach

    Page(s): 726 - 735
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    In this paper, we propose use of the multivalued operator theory to obtain a unifying approach to analysis of electronic circuits having “hysteresis-type” multivalued dc characteristics. We also show how multivalued operator theory can be successfully applied in analysis of dynamic circuits (e.g., oscillators). The proposed approach, although relying on very involved mathematics, enables formulation of very simple design and analysis formulae which can be used in a straightforward manner by an engineer with even a very fragmentary mathematics background. Several examples of analysis of driving-point and transfer characteristics are shown. Examples of dynamic circuits involving multivalued characteristics are also included View full abstract»

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  • Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits

    Page(s): 810 - 817
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    The advantages of CMOS differential-stack current-mode logic techniques together with the load-driving capability, switching speed, and noise immunity of bipolar devices has been exploited to develop a novel enhanced folded source coupled logic (FSCL) technique. A pair of quiet low-impedance push-pull load steering emitter followers (EF's) are implemented at the mutually complementary outputs of the CMOS FSCL (CFSCL) gate to obtain the EF2SCL gate structure. This modification considerably improves the performance of the gate at low supply voltages for a mixed-mode environment (e.g., ΣΔ data converters in digital audio, video, and radio frequency applications) without the cost of substantial power-supply spikes. Thorough current steering and dynamic-charge storage analysis at 100 MHz, using a 3.3-V supply voltage and BSIM process parameters was performed to evaluate the performance enhancement achievable by the EF2SCL technique. A 4-bit carry-lookahead with carry skip was achieved in 2 ns using a single EF2SCL logic gate, compared to 9 ns for a CFSCL gate. In addition, the deterioration of the voltage-swing (and hence the noise margin) with power-supply scaling and increased differential logic input stack-size is considerably more pronounced in a CFSCL gate compared to an EF2SCL gate. EF2SCL thus permits logic implementation using fewer stages compared to CFSCL, and hence reduces delay latency in a pipelined system. A tiny chip using MOSIS Orbit 2-μm n-well analog CMOS process (which provides a p-base diffusion layer for low-cost n-p-n device option) was used for the experimental verification View full abstract»

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  • Eigenfilter design of real and complex coefficient QMF prototypes

    Page(s): 787 - 792
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    In this brief, we propose a new method to design pseudo-QMF prototypes to implement near perfect reconstruction (NPR) modulated filter banks. The proposed method is based on the eigenfilter approach, simple to implement, but nevertheless, very efficient in designing high attenuation filters. The method also allows one to design complex coefficient prototypes that may be used to build nonuniform filter banks. Several examples of both uniform and nonuniform filter bank design are presented View full abstract»

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  • Constrained FIR filter design by the method of vector space projections

    Page(s): 714 - 725
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    A new technique for designing linear and arbitrary-phase finite-impulse response (FIR) filters with various types of constraints is proposed. The approach is based on the method of vector space projections. We describe the constraint sets and their associated projections that capture the properties of the desired filters. In filter design, as in many other engineering problems, one is primarily interested in meeting design constraints, i.e., finding a feasible solution, not necessarily an optimum one. Vector space projection methods are well-suited for this purpose. We furnish numerous examples of FIR filter design by vector space projections, including the important and difficult arbitrary phase/magnitude problem. Examples that demonstrate the advantages and flexibility of this method over other known methods are furnished View full abstract»

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  • An on-chip clock-adjusting circuit with sub-100-ps resolution for a high-speed DRAM interface

    Page(s): 771 - 775
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    A novel fully digital fine-delay circuit for a high-speed DRAM interface is proposed. The circuit consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element (squeezer) in the delay component converges the variations of the resolution. A test device design using 0.35-μm technology demonstrates that a resolution of 26 ps can be achieved. A clock-recovery circuit using this circuit has a two-clock-cycle lock time and sub-100-ps error View full abstract»

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  • Connecting partitioned frequency-domain filters in parallel or in cascade

    Page(s): 685 - 698
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    The efficient implementation of connected filters is an important issue in signal processing. A typical example is the cascade of two filters, e.g., an adaptive filter with a time-invariant prefilter. The filtering and adaptation is carried out very efficiently in the frequency domain whenever filters with many coefficients are required. This is implemented as a block algorithm by using overlap-save or overlap-add techniques. However, in many real-time applications also, a short latency time through the system is required, which leads to a degradation of the computational efficiency. Partitioned frequency-domain adaptive filters, also known as multidelay adaptive filters, provide an efficient way for the filtering and adaptation with long filters maintaining short processing delays. This paper shows a computationally efficient way of implementing two or more partitioned frequency-domain filters in cascade or in parallel when their filter lengths are large. The methods presented require only one fast Fourier transform (FFT) and one inverse fast Fourier transform per input and output port, respectively. The FFT size can be even smaller than the length of the filters, The filters can be either time invariant or adaptive View full abstract»

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  • Intrinsic stability-control method for recursive filters and neural networks

    Page(s): 797 - 802
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    Linear recursive filters can be adapted on-line but with instability problems. Stability-control techniques exist, but they are either computationally expensive or nonrobust. For the nonlinear ease, e.g., locally recurrent neural networks, the stability of infinite-impulse response (IIR) synapses is often a condition to be satisfied. This brief considers the known reparametrization-for-stability method for the on-line adaptation of IIR adaptive filters. A new technique is also presented, based on the further adaptation of the squashing function, which allows one to improve the convergence performance. The proposed method can be applied to various filter realizations (direct forms, cascade or parallel second order sections, lattice form), as well as to locally recurrent neural networks, such as the IIR multi-layer perceptron (IIR-MLP), with improved performance with respect to other techniques and to the case of no stability control. In this brief, the case of normalized lattice filters is particularly considered; an analysis of the stabilization effects is also presented both analytically and experimentally View full abstract»

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  • Minimum input sensitivity of high-order multi-stage sigma-delta modulator with first-order front-end

    Page(s): 792 - 796
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    Employing multi-stage sigma-delta modulators has provided an effective means of eliminating stability problems while achieving high-resolution analog to-digital conversion. However, component matching has become more stringent than a single stage modulator. Mismatches cause loss in the modulators signal to-noise ratio (SNR), but to a certain class of multi- stage modulators, discontinuity is also apparent in its SNR characteristics. This class of modulators employs a first-order modulator in its first stage. The discontinuity is caused by the nonlinearity of a first-order modulator's noise, which is related to the minimum input requirement for the first-order modulator. This brief includes the formulation of the first-order modulator's minimum amplitude, nonlinear characteristics, and its effect on multi-stage modulators View full abstract»

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  • Improved switched-capacitor interpolators with reduced sample-and-hold effects

    Page(s): 665 - 684
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (764 KB)  

    This paper proposes improved switched-capacitor (SC) interpolators using a novel sampling technique which eliminates the undesired distortion due to the sample-and-hold shaping effect at the lower input sampling rate. Such a sampling technique not only leads to a precise analog interpolation, as its digital counterpart does, but also allows to simplify the design procedures and resulting SC circuit implementations. Different circuit topologies with both finite- and infinite-impulse response characteristics are developed, respectively, for low- and high-selectivity filtering. Practical implementation issues are discussed with respect to capacitance ratio mismatches, as well as finite gain, bandwidth, and offset sensitivity effects of operational amplifiers. Besides detailed computer-based analyses, experimental results obtained from discrete component prototypes are also presented to demonstrate the proposed circuits View full abstract»

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  • An optimum SNS-to-binary conversion algorithm and pipelined field-programmable logic design

    Page(s): 736 - 745
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    The Optimum Symmetrical Number System (OSNS) formulation is a direct consequence of the need to extract the maximum amount of information from a symmetrically folded waveform, and has found use in applications such as folding analog-to-digital converters and phase-sampled direction finding antenna architectures. One of the key problems in an OSNS hardware realization is recombining the OSNS symmetrical residues (S1,S2,...S3) to determine the unknown incoming value. The symmetrical residues cannot be converted (e.g., using the Chinese Remainder Theorem) in a straightforward manner, since the integers within each modulus are ambiguous. This paper presents an OSNS-to-binary conversion algorithm for N=3 moduli of the form m1=2k+1, m2=2k, and m3=2k-1. The algorithm consists of three main steps: 1) conversion of the symmetrical residues into complete residues; 2) solving the resulting congruences in binary; and 3) determining the unknown incoming value. A B=14-bit pipelined field-programmable logic design (FPLD) using Fe=6 is also presented to illustrate the algorithm. The number of bits throughout the FPLD are quantified and an example calculation is worked out to numerically demonstrate the efficiency of the design View full abstract»

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  • Programmable fractional sample delay filters with flatness compromise between magnitude response and group delay

    Page(s): 783 - 787
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    In this paper, a new design of fractional sample delay filter is presented. This method is based on the Stancu polynomial, which possesses an extra parameter α. Under special choice of this parameter, the results obtained are identical to previous ones based on Lagrange interpolation formula. Much more flatness of group-delay response can be achieved at the sacrifice of the filter magnitude response. Thus, this method provides designers with more flexibility for trading between these two performance criteria View full abstract»

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  • Fast non-recursive computation of individual running harmonics

    Page(s): 779 - 782
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    It has been recently shown that the fast Fourier transform of a sequence which slides over a time-limited rectangular window can be carried out in a nonrecursive manner by means of O(N) computations. When only certain individual harmonics are needed, the application of this technique leads to O(log2 N) additions and O(log2 N) multiplications per harmonic. In this paper, an improvement is proposed by which any harmonic can be calculated at a cost of O(log2 N) additions but only two complex multiplications. The new technique stems from the application of the frequency-shifting property to existing methods View full abstract»

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  • On optimal ambiguity resistant precoders in ISI/multipath cancellation

    Page(s): 746 - 756
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    Ambiguity resistant (AR) precoding has recently been proposed in intersymbol interference (ISI) and multipath cancellations, where the ISI/multipath channel may have frequency-selective fading characteristics and its knowledge is not necessarily known. With the AR precoding, no diversity is necessary at the receiver. In the precoding, the AR property for a precoder plays an important rule. In this paper, more families and properties of AR precoders are presented and characterized. In particular, all systematic AR precoders are characterized. More importantly, we introduce the concepts of precoder distance and optimal precoders, and characterize and construct all optimal systematic AR precoders, when additive channel random noise is concerned. A necessary and sufficient condition for an AR precoder to be optimal is given, which is easy to check. With the optimal precoders, numerical simulations are presented to show the improved performance over the known AR precoders in ISI cancellation applications View full abstract»

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  • Low-voltage op amp design and differential difference amplifier design using linear transconductor with resistor input

    Page(s): 776 - 778
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    This paper describes a 1-V wide-input range and high linearity transconductance input stage that uses poly resistor and input-impedance boosting technique. Using the proposed transconductor, an op amp and a differential difference amplifier (DDA) were implemented in a 1.2-μm CMOS process. The transconductor has a total harmonic distortion (THD) of less than -60 dB for an input swing of 400 mV at 10 kHz. The op amp and the DDA show a peak-to-peak output swing of 800 mV and a THD of less than -70 dB for an output swing of 600 mV at 10 kHz View full abstract»

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  • Systematic analysis and modeling of integrated inductors and transformers in RF IC design

    Page(s): 699 - 713
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    An efficient modeling technique and a novel CAD tool for the accurate prediction of the performance of integrated inductors and transformers is presented. This generic and process-independent approach generates lumped-element models that easily plug into the RF IC design flow. Their accuracy is established through comparisons with measurements of numerous fabricated inductor structures. This paper intends to provide answers to vital questions in regard to existing limits and future expectations of the performance of on-chip inductors using comprehensive nomographs and quantitative analysis of spiral inductor families. An LNA design paradigm depicts how first-time-working silicon can be achieved when on-chip inductors' coupling is taken into account during the layout design process, minimizing risk, time, and cost View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope