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Circuits, Devices and Systems, IEE Proceedings -

Issue 4 • Date Aug 2000

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Displaying Results 1 - 9 of 9
  • IEE proceedings circuits, devices and systems

    Publication Year: 2000 , Page(s): 0_1 - 0_2
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

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  • Multi-level optimisation approach to switched capacitor filter synthesis

    Publication Year: 2000 , Page(s): 243 - 249
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (660 KB)  

    A multi-level optimisation approach to switched capacitor filter synthesis in which the top-down synthesis flow consists of high level and circuit level optimisers is presented. At high level, generalised macromodels of switched capacitor filter circuits are optimised to meet the given filter specifications. Parameters optimised at high level are treated as specifications for a circuit level optimiser, which is based on a novel algorithm that combines evolution strategies (ES) with simulated annealing. The optimisation strategy combines the advantages of SPICE-type simulations, neural performance models and knowledge-based approach in satisfying the constraints and specifications. The algorithmic details of the synthesis system are discussed in detail, and illustrative examples that demonstrate the validity of the approach are presented View full abstract»

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  • Current-mode group-delay equalisation using pole-zero mirroring technique

    Publication Year: 2000 , Page(s): 257 - 263
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    The authors describe an efficient method for designing current-mode group-delay equalisers. The method is based on introducing zeros into the right-hand s-plane by mirroring the poles of an LC ladder network. This is achieved by developing a current-mode model capable of implementing the pole-zero mirroring technique. Using multiple-output OTAs and grounded capacitors, the model is used to derive an nth-order active group-delay equaliser structure which is simpler, has better correction accuracy and is less sensitive when compared to cascade approach based equalisers. The equaliser design involves two optimisation algorithms. The first algorithm generates a polynomial function whose group-delay response equalises the filter response. The second algorithm produces the equaliser component values as a result of solving a set of nonlinear equations generated from coefficient matching the equaliser transfer function to the polynomial generated from the first algorithm. Simulated results with CMOS OTAs and measured results based on discrete realisation of a 6th-order equaliser are included. The results demonstrate that the equaliser can effectively compensate the delay characteristics of a 7th-order 5.75 MHz lowpass elliptic video filter to <5 ns ripple over 90% of the filter passband View full abstract»

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  • Increasing storage capacity in multilevel memory cells by means of communications and signal processing techniques

    Publication Year: 2000 , Page(s): 229 - 236
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    Multilevel and analogue memory cells have the capability of storing considerably more than one bit of information per cell. The number of levels the memory cells can store is limited by noise and bit error probability. The authors propose using error correction coding and digital modulation techniques used in communication systems to increase the storage capacity of multilevel and analogue memory cells. They evaluate these techniques and find that compared to the methods that do not use coded modulation techniques, typically, one extra bit per cell (i.e. effectively doubling the number of levels per cell) in storage capacity can be achieved. The techniques can also be applied to improve readout bit-error probability and provide unequal error protection for the bits to be stored. The latter technique is important for the efficient storage of digitised multimedia signals such as speech, audio, image and video signals. One- and two-dimensional coded modulation schemes as well as uncoded multilevel digital modulation schemes are presented in detail. Complexity and speed issues are also considered View full abstract»

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  • LADISPICE-1.2: a nonplanar-drift lateral DMOS transistor model and its application to power IC TCAD

    Publication Year: 2000 , Page(s): 219 - 227
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    A circuit simulation program (LADISPICE: LAteral Dmos transistor SPICE) has been developed for simulation and optimisation of power ICs which combine high-power lateral double-diffused MOS transistors with low-voltage logic and control elements on the same chip. This is a development of a previous static model and involves a charge-based dynamic model and a parasitic bipolar junction transistor model. These models have been incorporated into SPICE2G.6 source code and the paper demonstrates the excellent results. This new software represents an effective TCAD tool for the design and simulation of LDMOST power ICs View full abstract»

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  • Fast time domain simulation of generic resonant mode power converter: mapping the stability region

    Publication Year: 2000 , Page(s): 211 - 218
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    A macromodelling technique for generic resonant-mode power converters is described. This technique enables the transient and frequency analyses of resonant converters, embedded in their control circuitry, to be carried out some three orders of magnitude faster than by full component-level circuit simulation. This increase in speed enables `an analysis' to be treated as a primitive operation and allows more complex interactions of an entire system to be explored. The paper describes the technique, and demonstrates the power of the idea with a much higher level analysis; a resonant-mode converter controlled by a feedback system, driving a complex load. Like any physical system of this nature, there are combinations of system parameters that can cause overall instability (oscillation). In a power conversion environment, this can be extremely dangerous. The example shown uses a three-component load (R, L, C) and generates the `stability surface' in {R, L, C} space that separates the stable from the unstable regions of overall operation. This also demonstrates that the volume of `component space' enclosed by the stability surface decreases monotonically with increasing system phase margin View full abstract»

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  • Analogue discrete-time basic structures for adaptive IIR filters

    Publication Year: 2000 , Page(s): 250 - 256
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    An analogue discrete-time implementation of an adaptive infinite-impulse-response (IIR) filter is presented. The filter structure uses the IIR modelling capability of first- and second-order filter sections and the adaptation process is a variable step-size version of the least-mean-squared (LMS) algorithm. The gradient signals were chosen to allow the use of the whole dynamic range of the four-quadrant analogue multiplier. With respect to implementation problems, the effects of nonidealities on the building elements are investigated and reduced using appropriate circuit techniques. The functional behaviour of the proposed structure is demonstrated for a low-complexity third-order adaptive filter with a parallel architecture View full abstract»

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  • Sensitivity study and improvements on a nonlinear resistive-type neuron circuit

    Publication Year: 2000 , Page(s): 237 - 242
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (708 KB)  

    A generalised VLSI circuit realisation for a nonlinear active resistor-type neuron is proposed that implements a saturating sigmoidal-like function by combining the nonlinear characteristics of NMOS and PMOS transistors. The circuit design is based on using a parameter sensitivity analysis to develop a robust design that will be relatively insensitive to process-parameter variations over the area of the die. The nonlinear resistor has been integrated into a module which realises a programmable digital synaptic weight capability. A neuron is effectively formed from the parallel interconnection that takes place as multiplier outputs are connected to create an input node to the resultant distributed neuron. Designs in 0.35 and 0.8 μm processes are compared with a conservative 1.2 μm CMOS implementation View full abstract»

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  • Generalised k-variable-mixed-polarity Reed-Muller expansions for system of Boolean functions and their minimisation

    Publication Year: 2000 , Page(s): 201 - 210
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1000 KB)  

    A lookup table based method to minimise generalised partially-mixed-polarity Reed-Muller (GPMPRM) expansions with k mixed polarity variables is presented. The developed algorithm can produce solutions based on the desired cost criteria for the systems of completely specified functions. A heuristic approach based on the exclusion rule is adopted to extract the best dual polarity variables from any fixed polarity Reed-Muller (FPRM) expansion. The obtained experimental results compared favourably with the recently published results and outperform those generated by the exact minimal FPRM expansion minimisers View full abstract»

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