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Computers, IEEE Transactions on

Issue 5 • Date May 2000

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Displaying Results 1 - 10 of 10
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  • Is a bird in the hand worth more than two in the bush? Limitations of priority cognizance in conflict resolution for firm real-time database systems

    Page(s): 482 - 502
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    After a “boom” period from the late 80s to the early 90s, there appears to have been a reduction in the amount of work published on Concurrency Control (CC) in real-time database systems (RTDBS) in general and firm RTDBS in particular. This may be because existing paradigms (e.g., Optimistic CC) have been pushed to their limits and it is difficult to extract additional meaningful performance. One of the last unresolved bastions of real-time CC is the successful incorporation of priority cognizance. Researchers have speculated that priority cognizant optimistic concurrency control (OCC) algorithms, if designed well, could outperform priority insensitive ones in real-time database systems. So far, however, there is a distinct lack of conclusive proof available on this topic and the priority cognizant OCC algorithms that have appeared so far in the literature cannot claim unilateral superiority over their priority insensitive relatives. We thus surmise that successful incorporation of priority cognizance may lead to an increase in the performance of OCC protocols in firm RTDBSs. Based on this premise, we analyze the issue of priority cognizance and identify a critical condition that must hold for priority cognizant conflict resolution to work. The condition is that, on the average, the conflict sets of validating transactions should have a “large” number of transactions: We call this a bird in hand more than two in the bush phenomenon. Subsequently, we design a smart priority cognizant OCC variant, which we call OCC-APR, and analyze its performance, as well as that of several other concurrency control algorithms across a wide range of resource contention and system loading parameters. Surprisingly, it turns out that it is very difficult for priority cognizance to work as the above mentioned condition does not, usually,hold. We explain why this occurs and conclude that priority cognizance does not appear to be a promising technique to increase real-time CC performance. The contribution of this paper, thus, is to have laid to rest the “priority cognizance” issue with regard to real-time CCMs View full abstract»

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  • Mastrovito multiplier for general irreducible polynomials

    Page(s): 503 - 518
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    We present a new formulation of the Mastrovito multiplication matrix for the field GF(2m) generated by an arbitrary irreducible polynomial. We study in detail several specific types of irreducible polynomials, e.g., trinomials, all-one-polynomials, and equally-spaced-polynomials, and obtain the time and space complexity of these designs. Particular examples illustrating the properties of the proposed architecture are also given. The complexity results established in this paper match the best complexity results known to date. The most important new result is the space complexity of the Mastrovito multiplier for an equally-spaced-polynomial, which is found as (m2 -Δ) XOR gates and m2 AND gates, where Δ is the spacing factor View full abstract»

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  • An architecture for computing Zech's logarithms in GF(2m)

    Page(s): 519 - 524
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    In this paper, a new method for calculation of Zech's logarithm in GF(2m) is presented. For a given element, the logarithm is calculated by bit operations performed on its binary representation. No look-up tables are used. The proposed method makes feasible the implementation of an universal-type device for finite field arithmetic View full abstract»

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  • An efficient and scalable approach for implementing fault-tolerant DSM architectures

    Page(s): 414 - 430
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    Distributed Shared Memory (DSM) architectures are attractive to execute high performance parallel applications. Made up of a large number of components, these architectures have however a high probability of failure. We propose a protocol to tolerate node failures in cache-based DSM architectures. The proposed solution is based on backward error recovery and consists of an extension to the existing coherence protocol to manage data used by processors for the computation and recovery data used for fault tolerance. This approach can be applied to both Cache Only Memory Architectures (COMA) and Shared Virtual Memory (SVM) systems. The implementation of the protocol in a COMA architecture has been evaluated by simulation. The protocol has also been implemented in an SVM system on a network of workstations. Both simulation results and measurements show that our solution is efficient and scalable View full abstract»

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  • AQUILA: an equivalence checking system for large sequential designs

    Page(s): 443 - 464
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    In this paper, we present a practical method for verifying the functional equivalence of two synchronous sequential designs. This tool is based on our earlier framework that uses Automatic Test Pattern Generation (ATPG) techniques for verification. By exploring the structural similarity between the two designs under verification, the complexity can be reduced substantially. We enhance our framework by three innovative features. First, we develop a local BDD-based technique which constructs Binary Decision Diagram (BDD) in terms of some internal signals, for identifying equivalent signal pairs. Second, we incorporate a technique called partial justification to explore not only combinational similarity, but also sequential similarity. This is particularly important when the two designs have a different number of flip-flops. Third, we extend our gate-to-gate equivalence checker for RTL-to-gate verification. Two major issues are considered in this extension: (1) how to model and utilize the external don't care information for verification; and (2) how to extract a subset of unreachable states to speed up the verification process. Compared with existing approaches based on symbolic Finite State Machine (FSM) traversal techniques, our approach is less vulnerable to the memory explosion problem and, therefore, is more suitable for a lot of real-life designs. Experimental results of verifying designs with hundreds of flip-flops will be presented to demonstrate the effectiveness of this approach View full abstract»

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  • Fault-tolerant processor arrays using additional bypass linking allocated by Graph-Node coloring

    Page(s): 431 - 442
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    An advanced spare-connection scheme for k-out-of-n redundancy called “generalized additional bypass linking” is proposed for constructing fault-tolerant massively parallel computers with series-connected, mesh-connected, or tree-connected processing element (PE) arrays. This scheme uses bypass links with wired OR connections to selectively connect the primary PEs to a spare PE in parallel. These bypass links are allocated to the primary PEs by node-coloring of a graph with a minimum inter-node distance of three in order to minimize the number of bypass links (i.e., the chromatic number). The main advantage of this scheme is that it can be used for constructing various k-out-of-n configurations capable of enhanced PE-to-PE communication and broadcast while still achieving strong fault tolerance for these PEs and links. In particular, it enables the construction of optimal r-strongly-fault-tolerant configurations capable of direct k-out-of-n selections by providing r spare PEs and r extra connections per PE for any kind of array when node-coloring with a distance of three is used. This simple spare-circuit structure enhances fault tolerance more than conventional schemes do. The node-coloring patterns were constructed using new node-coloring algorithms and the chromatic numbers were evaluated theoretically. Enhanced PE-to-PE communication and broadcast were achieved by using new fault-tolerant routing algorithms based on the properties of the node-coloring patterns with four or five message transmission steps being optimal configurations with any size array View full abstract»

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  • On the design of IEEE compliant floating point units

    Page(s): 398 - 413
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    Engineering design methodology recommends designing a system as follows: Start with an unambiguous specification, partition the system into blocks, specify the functionality of each block, design each block separately, and glue the blocks together. Verifying the correctness of an implementation then reduces to a local verification procedure. We apply this methodology for designing a provably correct IEEE rounding unit that can be used for various operations, such as addition and multiplication. First, we provide a mathematical and, hopefully, unambiguous definition of the IEEE Standard which specifies the functionality. We give explicit and concise rules for gluing the rounding unit with a floating-point adder and multiplier. We then present floating-point addition and multiplication algorithms that use the rounding unit. To the best of our knowledge, our design is the first publication that deals with detecting exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit in a floating point unit. Our abstraction level avoids bit-level representations and arguments to help clarify the functionality of the algorithm View full abstract»

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  • MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

    Page(s): 465 - 481
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2684 KB)  

    This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems View full abstract»

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  • A family of variable-precision interval arithmetic processors

    Page(s): 387 - 397
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    Traditional computer systems often suffer from roundoff error and catastrophic cancellation in floating point computations. These systems produce apparently high precision results with little or no indication of the accuracy. This paper presents hardware designs, arithmetic algorithms, and software support for a family of variable-precision, interval arithmetic processors. These processors give the programmer the ability to detect and, if desired, to correct implicit errors in finite precision numerical computations. They also provide the ability to solve problems that cannot be solved efficiently using traditional floating point computations. Execution time estimates indicate that these processors are two to three orders of magnitude faster than software packages that provide similar functionality View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au