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Semiconductor Manufacturing, IEEE Transactions on

Issue 3 • Date Aug 2000

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Displaying Results 1 - 18 of 18
  • A methodology for product mix planning in semiconductor foundry manufacturing

    Publication Year: 2000 , Page(s): 278 - 285
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    Since a semiconductor foundry plant manufactures a wide range of memory and logic products using the make-to-order business model, the product mix is an important production decision. This paper first describes the characteristics of the product mix planning problem in foundry manufacturing that are attributable to the long flow time and queuing network behaviors. The issues of time bucket selection, mix optimization and bottleneck-based planning are next addressed. A decision software system based on integer linear programming techniques and a heuristic procedure has been implemented for mix planning. Data provided by a wafer plant has been used to study problems related to product mix planning. It was determined that the suitable time bucket of planning is either one week or one month and the lead-time offset factor should be included in the logic of workload calculation. This paper also presents various facets of product mix decisions and how they should be integrated with operations management View full abstract»

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  • An analytical model of multiple ILD thickness variation induced by interaction of layout pattern and CMP process

    Publication Year: 2000 , Page(s): 286 - 292
    Cited by:  Papers (5)  |  Patents (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    In this paper, an analytical model for chemical mechanical polishing (CMP) is described. This model relates the physical parameters of the CMP process to the in-die variation of interlayer dielectric (ILD) in multilevel metal processes. The physical parameters considered in this model include the deposited ILD profile, deformation of the polishing pad and the hydrodynamic pressure of slurry flow. Model parameters are adjusted based on the first ILD layer and then applied to the upper ILD layers. Comparison of simulated results with sample data is performed at the die level of a state-of-the-art microprocessor View full abstract»

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  • Fault detection of plasma etchers using optical emission spectra

    Publication Year: 2000 , Page(s): 374 - 385
    Cited by:  Papers (40)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    The objective of this paper is to investigate the suitability of using optical emission spectroscopy (OES) for the fault detection and classification of plasma etchers. The OES sensor system used in this study can collect spectra at up to 512 different wavelengths. Multiple scans of the spectra are taken from a wafer, and the spectra data are available for multiple wafers. As a result, the amount of the OES data is typically large. This poses a difficulty in extracting relevant information for fault detection and classification. In this paper, we propose the use of multiway principal component analysis (PCA) to analyze the sensitivity of the multiple scans within a wafer with respect to typical faults such as etch stop, which is a fault that occurs when the polymer deposition rate is larger than the etch rate. Several PCA-based schemes are tested for the purpose of fault detection and wavelength selection. A sphere criterion is proposed for wavelength selection and compared with an existing method in the literature. To construct the final monitoring model, the OES data of selected wavelengths are properly scaled to calculate fault detection indices. Reduction in the number of wavelengths implies reduced cost for implementing the fault detection system. All experiments are conducted on an Applied Materials 5300 oxide etcher at Advanced Micro Devices (AMD) in Austin, TX View full abstract»

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  • Plasma etching optimization of oxide/nitride/oxide interpoly dielectric breakdown time in flash memory devices

    Publication Year: 2000 , Page(s): 386 - 389
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    The breakdown time of flash memory oxide/nitride/oxide (ONO) layer tbd under positive constant current stressing has been found to be closely related to the cumulative extent of (over)etch of the tungsten silicide, control polysilicon, and ONO layers, i.e., Σ(ΛOE). An empirical first-order relation between tbd and Σ(ΛOE) has been derived to facilitate the plasma etch recipe optimization. This has led to a four-fold increase in the average tbd across a 200-mm wafer to 208 s. More importantly, the spread in tbd has been tightened to ~5%, which is down from ~54% View full abstract»

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  • Implementation of modeling and simulation in semiconductor wafer fabrication with time constraints between wet etch and furnace operations

    Publication Year: 2000 , Page(s): 273 - 277
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    In semiconductor wafer fabrication, time constraints between process steps in furnace and wet etch make it difficult to achieve cycle time targets and maximize machine utilization. For capacity planning, it is difficult to estimate the impact of these time constraints on the machine capacity. Infineon Technologies Dresden has conducted a study using discrete event simulation, to investigate the actual situation in the factory and to identify recommendations to eliminate or to reduce the impart of time constraints. The work in this paper yields a two-day reduction in total cycle time after implementation of findings in the factory View full abstract»

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  • A control method to reduce the standard deviation of flow time in wafer fabrication

    Publication Year: 2000 , Page(s): 389 - 392
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB)  

    This paper proposes a control, method for reducing flow time variability in a wafer fabrication facility with multiple wafer types. We employ stochastic Petri nets to model and analyze the machine module, and define operation due dates using a novel utilization index metric. An operation due date (OPNDD) rule for lot dispatch is proposed and evaluated against other lot dispatch policies View full abstract»

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  • Wafer thermal desorption spectrometry in a rapid thermal processor using atmospheric pressure ionization mass spectrometry

    Publication Year: 2000 , Page(s): 315 - 321
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    This paper demonstrates the possibility of performing thermal desorption spectrometry (TDS) on wafers in an atmospheric pressure rapid thermal processor (RTP). A special gas sampling system is described, which allows the analysis of gas composition inside the RTP chamber with atmospheric pressure ionization mass spectrometry (APIMS). Sampling is controlled with no valve operation and high dilution of the sample gas flow can be achieved while maintaining a short sample transfer time. It is shown how gas flows can be optimized to improve the sensitivity and resolution of TDS spectra. The RTP-APIMS setup was used in a study of H 2O absorption by low dielectric constant fluorinated silica glass (FSG) films, helping to develop a cap that reduced H2O absorption upon storage by a factor of 60. NH3 is shown to desorb from FSG and SiO2 films deposited by plasma-enhanced chemical vapor deposition (PECVD), which may be of concern for the reliability of integrated circuits View full abstract»

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  • Focus characterization using end of line metrology

    Publication Year: 2000 , Page(s): 322 - 330
    Cited by:  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB)  

    A new method is introduced to measure relative focus using conventional optical overlay instruments. Optical end of line metrology (OELM), is based on patterning a wide frame in which adjacent sides are constructed of submicron sized lines that run perpendicular to the center opening. Because truncation is size dependent, line and space features exhibit significantly more line shortening effects than the solid sections. When measured with a conventional optical overlay tool, the difference in line shortening between the solid and line and space sections are measured as an alignment offset, which is a relative measure of actual line shortening. Reproducibility for measuring the apparent misalignment of these modified box-in-box structures was 3 nm (3σest), which is similar to the repeatability for measuring conventional resist box in box alignment boxes. Truncation is sensitive to focus and the utility for using OELM toward characterizing focus-dependent lens parameters was investigated. Estimated 3σ for calculating best focus and astigmatism were 0.04 μm and 0.01 μm, respectively. Focus corrections were accurate to 0.05 μm within ±0.3 μm of best focus. Additionally, a general method is presented to estimate the error in the calculated best focus View full abstract»

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  • A new gas circulation RIE

    Publication Year: 2000 , Page(s): 310 - 314
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    A new gas circulation RIE has been developed. It pumps the exhausted gas still containing usable process gas into the RIE process chamber to be reused. This new gas circulation RIE showed performances of etch rate, selectivity, etching profile, and uniformity in C4 F8/CO/Ar SiO2 etching process comparable to those for the conventional process with 50% less C4F8 and 80% less CO and Ar of the original input gas flow rates. It also decreased PFC emission by two thirds less in CO2 conversion. This new gas circulation RIE is effective for the suppression of the greenhouse effect and etching process cost View full abstract»

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  • SHEWMA: an end-of-line SPC scheme using wafer acceptance test data

    Publication Year: 2000 , Page(s): 344 - 358
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    In this paper, an end-of-line quality control scheme based on wafer acceptance test (WAT) data is presented. Due to the multiple-stream and sequence-disorder effects typically present in the WAT data, an abnormal process shift caused by one machine at an in-line step may become vague for detection using end-of-line WAT data. A methodology for generating robust design parameters for the simultaneous application of Shewhart and EWMA control charts to WAT data is proposed. This SHEWMA scheme is implemented in a foundry environment and its detection and diagnosis-enhancing capabilities are validated using both numerical derivations and fab data. Results show that the SHEWMA scheme is superior to the current practices in detection speed. Its use is complementary to the existing in-line SPC for process integration View full abstract»

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  • The cleaning at a back surface and edge of a wafer for introducing Cu metallization process

    Publication Year: 2000 , Page(s): 300 - 304
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    Cu metallization has been introduced in high-speed complementary metal-oxide-semiconductor (CMOS) large scale integration (LSI) in order to achieve low electrical resistivity. This means Cu contamination can be spread all over semiconductor equipment by the wafers, even though Cu has been thoroughly eliminated from semiconductor manufacturing for a long time. To protect the other wafers without Cu from Cu cross-contamination, we have demonstrated a method that can clean the back surface and selectively clean the edge of a wafer simultaneously without any masks. This method performs the cleaning by optimizing the overhang of chemicals in the single-wafer system with the Bernoulli chuck. We have also demonstrated a new edge extractor that can be used to perform the quantitative evaluation of Cu contamination at the wafer edge. The combination of the edge cleaning and the edge evaluation is useful for introducing not only Cu, but also new exotic materials such as Ta2O5 and BST View full abstract»

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  • Device dependent control of chemical-mechanical polishing of dielectric films

    Publication Year: 2000 , Page(s): 331 - 343
    Cited by:  Papers (18)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    This paper presents a control scheme for run-to-run control of chemical-mechanical polishing (CMP). The control scheme tracks both device pattern dependent and equipment induced disturbances. The structure of the controller is such that sensitivity to qual (unpatterned blanket oxide) wafer frequency is minimized. Additionally, prethickness variation and metrology delay are accounted for in the design. Results from applying this scheme in volume production are presented View full abstract»

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  • Segment-based approach for real-time reactive rescheduling for automatic manufacturing control

    Publication Year: 2000 , Page(s): 264 - 272
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    We propose a new segment-based approach for a real-time reactive rescheduling method. The approach is applicable to actual large-scale manufacturing systems, such as fully automated semiconductor wafer fabrication lines. The proposed method can efficiently (in terms of computation time) schedule processing operations at equipment units by dividing a wide scheduling range into small segments and by using a greedy scheduling algorithm. It can also reactivate infeasible schedules without sacrificing the quality of schedules in terms of productivity as much as possible. From the simulation results obtained, we experimentally confirmed that the proposed method reactivates, without significant productivity loss caused by the rescheduling algorithm itself, infeasible schedules faster than a comparative method commonly in use today. Consequently, the proposed method manages to keep schedules at each equipment unit executable in terms of processing performance and schedule quality View full abstract»

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  • A new method for treating fluorine wastewater to reduce sludge and running costs

    Publication Year: 2000 , Page(s): 305 - 309
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    Reduction of the sludge generated in fluorine wastewater treatment is a critical problem for the semiconductor industry. We have developed a new method for treating fluorine wastewater in order to reduce sludge and running costs. This method utilizes a small amount of Al(OH)3 not only as an aggregator for CaF2 generated from fluoride ions in the wastewater but also as an effective fluorine adsorbent. The Al(OH)3 as fluorine adsorbent is used repeatedly through an AI(OH)3 reclamation process. This method can effectively treat the concentrated fluorine wastewater to achieve an exceedingly low concentration in one-step treatment. We constructed a practical treatment system using this method by modifying part of an existing conventional system. This new treatment system is able to reduce both the total sludge and running costs to about one-tenth those of a conventional system View full abstract»

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  • A study in dynamic neural control of semiconductor fabrication processes

    Publication Year: 2000 , Page(s): 359 - 365
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    This paper describes a generic dynamic control system designed for use in semiconductor fabrication process control. The controller is designed for any batch silicon wafer process that is run on equipment having a high number of variables that are under operator control. These controlled variables include both equipment state variables such as power, temperature, etc., and the repair, replacement, or maintenance of equipment parts, which cause parameter drift of the machine over time. The controller consists of three principal components: 1) an automatically updating database, 2) a neural-network prediction model for the prediction of process quality based on both equipment state variables and parts usage, and 3) an optimization algorithm designed to determine the optimal change of controllable inputs that yield a reduced operation cost, in-control solution. The optimizer suggests a set of least cost and least effort alternatives for the equipment engineer or operator. The controller is a PC-driven software solution that resides outside the equipment and does not mandate implementation of recommendations in order to function correctly. The neural model base continues to learn and improve over time. An example of the dynamic process control tool performance is presented retrospectively for a plasma etch system. In this study, the neural networks exhibited overall accuracy to within 20% of the observed values of .986, .938, and .87 for the output quality variables of etch rate, standard deviation, and selectivity, respectively, based on a total sample size of 148 records. The control unit was able to accurately detect the need for parts replacements and wet clean operations in 34 of 40 operations. The controller suggested chamber state variable changes which either improved performance of the output quality variables or adjusted the input variable to a lower cost level without impairment of output quality View full abstract»

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  • Application of CMP process monitor to Cu polishing

    Publication Year: 2000 , Page(s): 293 - 299
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    We have developed a chemical mechanical polishing (CMP) process monitor which uses polishing vibration. The monitor enables us to accurately detect the polishing end point in copper (Cu) polishing even when the process conditions such as initial film thickness, slurry flow and polishing rate are changed and when polishing multilayer film. Furthermore, the monitor is not only applicable to Cu polishing but also to planarizing polishing of an inter-level dielectric layer. The monitor can be also used to control the processes and the equipment because of its capability to detect abnormalities in the polishing conditions View full abstract»

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  • Particle characteristics of 300-mm minienvironment (FOUP and LPU)

    Publication Year: 2000 , Page(s): 259 - 263
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    We have clarified the particle characteristics of a front opening unified pod (FOUP) and a load port unit (LPU) experimentally. The FOUP and LPU are fundamental components in 300-mm minienvironment systems. Our experiments showed the following. The particles per wafer pass (PWP) increases with the number of airborne particles outside the enclosure. The particle characteristics of FOUP and LPU can be improved by reducing the FOUP door-opening speed. The PWP of the wafer in the top slot is remarkably high. By optimizing the FOUP door-opening speed, we can achieve FOUP and LPU particle characteristics similar to those of a standard mechanical interface (SMIF) system View full abstract»

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  • A neural-network approach to recognize defect spatial pattern in semiconductor fabrication

    Publication Year: 2000 , Page(s): 366 - 373
    Cited by:  Papers (54)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    Yield enhancement in semiconductor fabrication is important. Even though IC yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form spatial patterns, it is usually a clue for the identification of equipment problems or process variations. This research intends to develop an intelligent system, which will recognize defect spatial patterns to aid in the diagnosis of failure causes. The neural-network architecture named adaptive resonance theory network 1 (ART1) was adopted for this purpose. Actual data obtained from a semiconductor manufacturing company in Taiwan were used in experiments with the proposed system. Comparison between ART1 and another unsupervised neural network, self-organizing map (SOM), was also conducted. The results show that ART1 architecture can recognize the similar defect spatial patterns more easily and correctly View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
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1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721