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Electron Devices, IEEE Transactions on

Issue 8 • Date Aug 2000

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Displaying Results 1 - 22 of 22
  • Comparison of deep-submicrometer conventional and retrograde n-MOSFETs

    Page(s): 1573 - 1579
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    An extensive comparison of the deep-submicrometer conventional and retrograde n-MOSFETs designed for either a low-power or a high-performance technology is made. We compare simulated curves of off-current versus channel length (IOFF-L) and on-current vs. channel length (ION-L). We include parametric dependence upon the channel length L, and aspects of the doping profile, namely surface doping NS, bulk doping NB, and depth of the lightly doped surface layer d. At a given L, the comparison of structures with the same ION shows that all retrograde profiles exhibit much worse IOFF. On the other hand, comparison of structures with the same IOFF shows that all retrograde profiles have lower ION. Moreover, judging the short-channel advantages of a proposed device structure based upon the V T-L roll-off curve without examination of the related IOFF-L and ION-L curves could lead to a mistaken technology assessment View full abstract»

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  • Forward gated-diode measurement of filled traps in high-field stressed thin oxides

    Page(s): 1682 - 1683
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    The forward gated-diode monitoring technique can find its potential applications in assessing the filled traps in MOSFET thin oxides, which are subjected to high-field stressing and then followed by a hot-electrons filling scheme. Our measurement of the gate voltage shift associated with the forward current peak produces a power law relation between the filled trap density and the electron stress fluence, indeed in close agreement with that obtained by MOSFET threshold voltage shift View full abstract»

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  • Physical mechanisms limiting the manufacturing uniformity of millimeter-wave power InP HEMT's

    Page(s): 1560 - 1565
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    We have developed a methodology to diagnose the physical mechanisms limiting the manufacturing uniformity of millimeter-wave power InAlAs/InGaAs HEMT's on InP. A statistical analysis was carried out on dc figures of merit obtained from a large number of actual devices on an experimental wafer. correlation studies and principal component analysis of the results indicated that variations in Si delta-doping concentration introduced during molecular-beam epitaxy accounted for more than half of the manufacturing variance. Variations in the gate-source distance that is determined by the electron-beam alignment in the gate formation process were found to be the second leading source of manufacturing variance. The statistical methodology used in this work is suitable for continuous process yield diagnostics and improvement in a manufacturing environment View full abstract»

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  • Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

    Page(s): 1580 - 1586
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    High performance super TFTs with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decreases significantly when the device is scaled down, resulting in better device performance and higher uniformity View full abstract»

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  • Characteristics of polysilicon oxides combining N2O nitridation and CMP processes

    Page(s): 1545 - 1552
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    This paper present a high-quality polysilicon oxide combining N 2O nitridation and chemical mechanical polishing (CMP) processes. Experimental results indicate that polyoxide grown on the CMP sample exhibits a lower leakage current, higher dielectric breakdown field, higher electron barrier height, less electron trapping rate, higher charge-to-breakdown (Qbd), and lower density of trapping charge than those of non-CMP samples. In addition, the CMP process enhances nitrogen incorporation at the interface by the N2 O nitridation, ultimately improving the polyoxide quality. However, the CMP process smooths the surface of polysilicon and this planar surface reduces the out-diffusion of the phosphorous during thermal oxidation View full abstract»

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  • Technologies to improve photo-sensitivity and reduce VOD shutter voltage for CCD image sensors

    Page(s): 1566 - 1572
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    New technologies to increase the photo-sensitivity and reduce the shutter voltage of the vertical over-flow-drain (VOD) have been developed for CCD image sensors. The photo-sensitivity was increased 40% by forming an anti-reflection film over the photodiode and reducing the thickness of the p+-layer formed at the photodiode surface. The VOD shutter voltage was reduced from 31 to 18 V by using an epitaxially grown substrate with double impurity concentration layers View full abstract»

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  • Study of the extended p+ dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFET's

    Page(s): 1678 - 1680
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    Simulation results on a novel extended p+ dual source SOI MOSFET are reported. It is shown that the presence of the extended p + region on the source side, which can he fabricated using post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the length of the extended p+ region is half the channel length, the improvement in breakdown voltage is about 120% when compared to the conventional SOI MOSFET's View full abstract»

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  • Analytical theory of semiconductor p-n junctions and the transition between depletion and quasineutral region

    Page(s): 1624 - 1629
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    We show that the standard model of p-n junctions, which considers only insulating and metallic regions, is inadequate in a transition region that is significantly broader than a Debye length. We give analytical estimates of this length, the carrier densities and electric fields that match numerical simulation closely. We consider three regions of the diode as was suggested already by Shockley; the depletion region, the transition region extending to the point of zero electric field, and the base quasineutral region. Our analytical estimate helps to eliminate some paradoxes associated with the appearance of net charge in the quasineutral region and also explains contributions to the capacitive nature of the p-n junction and, for long diodes, the lack, of the usually predicted strong increase of the depletion capacitance in extreme forward bias View full abstract»

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  • A thorough study of quasi-breakdown phenomenon of thin gate oxide in dual-gate CMOSFET's

    Page(s): 1608 - 1616
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    The conduction mechanism of the quasibreakdown (QB) mode for thin gate oxide has been studied in a dual-gate CMOSFET with a 3.7 nm thick gate oxide. Systematic carrier separation experiments were conducted to investigate the evolutions of gate, source/drain, and substrate currents before and after gate oxide quasibreakdown (QB). Our experimental results clearly show that QB is due to the formation of a local physically-damaged-region (LPDR) at Si-SiO2 interface. At this region, the effective oxide thickness is reduced to the direct tunneling (DT) regime. The observed high gate leakage current is due to DT electron or hole currents through the region where the LPDR is generated. Twelve Vg, Isub, Isd/ versus time curves and forty eight I-V curves of carrier separation measurements have been demonstrated. All the curves can be explained in a unified way by the LPDR QB model and the proper interpretation of the carrier separation measurements. Particularly, under substrate injection stress condition, there is several orders of magnitude increase of Isub(Isd/) at the onset point of QB for n(p)-MOSFET, which mainly corresponds to valence electrons DT from the substrate to the gate, consequently, cold holes are left in the substrate and measured as substrate current. These cold holes have no contribution to the oxide breakdown and thus the lifetime of oxide after QB is very long. Under the gate injection stress condition, there is sudden drop and even change of sign of Isub(Isd/) at the onset point of QB for n(p)-MOSFET, which corresponds to the disappearance of impact ionization and the appearance of hole DT current from the substrate to the gate View full abstract»

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  • A dual body SOI structure for mixed analog-digital mode circuits

    Page(s): 1617 - 1623
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    A new silicon-on-insulator (SOI) structure for mixed analog-digital applications is proposed where analog and digital MOSFET's are independently optimized. Two types of field oxide are introduced so that the body bias of analog devices can be effectively controlled whereas the channel region for digital devices is fully depleted. From measurements of the body related device characteristics such as the output resistance, the variation of threshold voltage and transconductance, 1/f noise, body resistance, and the self-heating effect, it is shown that the proposed structure is promising for SOI technology in mixed analog-digital mode circuit applications View full abstract»

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  • Multiple-route and multiple-state current-voltage characteristics of an InP/AlInGaAs switch for multiple-valued logic applications

    Page(s): 1553 - 1559
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    A novel multiple-state switching device based on an InP/AlInGaAs heterojunction bipolar transistor (HBT) structure has been successfully fabricated and demonstrated. The common-emitter current gain up to 25 is obtained under the forward operation mode. However, the anomalous multiple-negative-differential-resistance (MNDR) phenomena controlled either by electrical or optical input signals are observed under the inverted operation mode. The studied device exhibits a single-route S-shaped NDR behavior in the dark and a distinct significant S-shaped MNDR phenomena by introducing an incident light source at room temperature. Moreover, the anomalous multiple-route and multiple-step current-voltage (I-V) characteristics are also observed at 77 K. The switching behaviors are attributed to the avalanche multiplication, barrier lowering effect and potential redistribution process. Experimental results show that the studied device provides a good potentiality for multiple-valued logic and optoelectronic switching system applications View full abstract»

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  • Frequency domain lifetime characterization

    Page(s): 1653 - 1661
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    Time-based measurements are commonly used for lifetime characterization of semiconductors. We have developed the theory, verified by experiment, of frequency-based lifetime characterization as an alternative to time-based measurements for MOS devices biased in inversion. One consideration during lifetime/diffusion length measurements, is whether the near-surface space-charge region or the bulk or quasineutral region is characterized. To characterize the near-surface space-charge region of the device, one usually makes room temperature pulsed MOS capacitor or diode leakage current measurements. We show that room-temperature, frequency-domain capacitance, conductance, or resistance measurements characterize the quasineutral bulk, not the space charge region, in contrast to room-temperature pulsed MOS-C or diode leakage current measurements which characterize the space-charge region View full abstract»

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  • A comparative study of gate direct tunneling and drain leakage currents in n-MOSFET's with sub-2 nm gate oxides

    Page(s): 1636 - 1644
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    This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents View full abstract»

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  • A dynamic-threshold SOI device with a J-FET embedded source structure and a merged body-bias-control transistor. II. Circuit simulation

    Page(s): 1593 - 1598
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    For pt.I see ibid., vol. 47, no.8, p.1587-92 (2000). A primary transistor having an embedded J-FET, or resistor, immediately under the source junction and a small subsidiary body-bias-control transistor enables the construction of a variable-threshold SOI MOSFET with a small area penalty and without any limitation on the power-supply voltage. The subsidiary transistor, synchronized with the gate input signal, injects charges into the body depending on the output-node transient condition and controls the body potential to increase the on-current and decrease the off-current. The embedded J-FET eliminates such floating-body effects as delay hysteresis. The inverter delay time with a 1-pF load capacitance can be shortened to 40% of that of a bulk device under I-V operation, A different embedded J-FET circuit construction under the source enables an NMOS pass gate to be constructed without the output-amplitude degradation caused by the source follower, with a switching speed higher than that of a conventional CMOS pass gate View full abstract»

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  • Analysis for charged spacers in FED

    Page(s): 1673 - 1677
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    Charged spacers in the field emission display (FED) are analyzed with the Monte Carlo method. The spacer is made of an insulator, which has generally a high secondary electron emission property. Under electron bombardment, the secondary electron emission induces charge on the spacer. We show that the surface of the spacer is charged positively in FED operation, which would cause an image distortion. We analyze the effect of charging on the spacer in terms of the electron density profile and luminescence profile of a dot near the spacer. Simulation results show that the image of a dot near the spacer is darker and smaller than that of a dot away from the spacer, though electrons are crowded near spacers. The results are confirmed by experiments. Finally, we suggest a way to reduce the effect of spacer charging by introducing a metal strip View full abstract»

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  • A transient SPICE model for digitally modulated RF characteristics of ion-implanted GaAs MESFET's

    Page(s): 1680 - 1681
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    A transient SPICE model, which was previously developed for epitaxial GaAs MESFET's, was modified for ion-implanted GaAs MESFET's. The model accounts for both trapping and detrapping effects hence can simulate both low-frequency dispersion and gate-lag characteristics. The model was experimentally verified in terms of pulsed current-voltage (I-V) characteristics and digitally modulated RF carrier waveforms View full abstract»

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  • Thin-film transistors in polycrystalline silicon by blanket and local source/drain hydrogen plasma-seeded crystallization

    Page(s): 1599 - 1607
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    Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625°C or 1000°C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600°C, have a linear field-effect mobility of ~35 cm2/Vs and an ON/OFF current ratio of ~106, and TFTs with a maximum process temperature of 1000°C, have a linear field-effect mobility of ~100 cm2/Vs and an ON/OFF current ratio of ~107. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600°C showed a nearly twofold improvement in mobility (72 versus 37 cm2 /Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current View full abstract»

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  • Ferroelectric neuron integrated circuits using SrBi2Ta 2O9-gate FET's and CMOS Schmitt-trigger oscillators

    Page(s): 1630 - 1635
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    A pulse frequency modulation (PFM) type ferroelectric neuron circuit composed of a metal-ferroelectric-semiconductor field effect transistor (MFSFET) and a CMOS Schmitt-trigger oscillator was fabricated on an SOI structure, in which SrBi2Ta2O9 (SBT) was used as a ferroelectric gate material of the FET. It was found that the fabricated MFSFET showed a relatively good ID-VG (drain current versus gate voltage) characteristic with a hysteresis loop due to the ferroelectricity of the SBT film and that it acted as a synapse device with adaptive-learning function. It was also found that the output pulse height of the circuit was as high as the power supply voltage and that output pulse frequency was changed as the number of applied input pulses increased View full abstract»

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  • A dynamic-threshold SOI device with a J-FET embedded source structure and a merged body-bias-control transistor. I. A J-FET embedded source structure properties

    Page(s): 1587 - 1592
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    The floating-body effects in SOI CMOSFETs are fully suppressed by embedding a J-FET source structure immediately beneath the source/drain junction. The drain of the J-FET consists of a Schottky barrier diode; the holes generated in the body can easily be ejected into the source through the forward-biasing of this diode. The source-drain breakdown voltage and drain-induced barrier-lowering characteristics of this device are the same as those of a bulk device. With this structure, the body potential syncrhronously couples to the gate bias in the dynamic mode without potential hysteresis when the body-to-source resistance is properly designed. The inverter-chain delay time should be 45% of that of a bulk device operating at 1 V without an excess load View full abstract»

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  • High performance 0.1 μm gate-length p-type SiGe MODFET's and MOS-MODFET's

    Page(s): 1645 - 1652
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    High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (gm) of 142 mS/mm, a unity current gain cut-off frequency (fT) of 45 GHz and a maximum oscillation frequency (fMAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO2 was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at Vgs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g m of 90 mS/mm, fT of 38 GHz, and fmax of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NFmin) of 1.29 dB and an associated power gain (Ga) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF min of 0.92 dB and a Ga of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications View full abstract»

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  • Increasing emission current from MIM cathodes by using an Ir-Pt-Au multilayer top electrode

    Page(s): 1667 - 1672
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    We investigated the effect of the top electrode materials on the electron emission and durability of metal-insulator-metal (MIM) cathodes. The durability is improved when high sublimation-enthalpy material, such as Ir, Mo, or W, are used; however, the emission current, and the transfer ratio, decrease. The material dependence of the transfer ratio is shown to be dominated by the scattering probability of hot electrons in the metal. The scattering probability was estimated from the metal's density-of-states, or more simply, from the number of d-electrons. We found that the multilayer top electrode consisting of Ir, Pt, and Au provides the best top electrode combination for MIM cathodes. The high sublimation-enthalpy Ir layer, which is in contact with the insulator, acts as a barrier metal and improves the durability, whereas the surface Au layer maintains the transfer ratio at a high value. With this top electrode structure, emission current density is increased to 5.8 mA/cm2, which is sufficient for field-emission displays. We demonstrated a display consisting of a 30×30-dot MIM cathode-array with the multilayer top electrodes View full abstract»

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  • A new trench base-shielded bipolar transistor

    Page(s): 1662 - 1666
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    In this paper, a new power bipolar transistor structure called the trench base-shielded bipolar transistor (TBSBT) Is proposed and experimentally demonstrated. This structure incorporates deep p+ poly-Si trenches into the base of a conventional bipolar transistor. With the base shielded effectively by the p+ trenches, the base of the TBSBT can be made very narrow to achieve high current gain hFE and high cut-off frequency fT without compromising on the breakdown voltage. Experimental results show that the on-state anti switching characteristics of the TBSBT are significantly better than those of the existing power bipolar transistors View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology