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IEE Proceedings - Computers and Digital Techniques

Issue 2 • Mar 2000

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Displaying Results 1 - 10 of 10
  • Hardware-software timing coverification of concurrent embedded real-time systems

    Publication Year: 2000, Page(s):83 - 92
    Cited by:  Papers (10)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (588 KB)

    The results of hardware-software codesign of concurrent embedded real-time systems are often not verified or not easily verifiable. This has serious consequences when high-assurance systems are codesigned. The main difficulty lies in the different time-scales of the embedded hardware, of the embedded software, and of the environment. This difference makes hardware-software timing coverification no... View full abstract»

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  • Cell-based implementation of radix-4/2 64b dividend 32b divisor signed integer divider using the COMPASS cell library

    Publication Year: 2000, Page(s):109 - 115
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (400 KB)

    A high-speed 64b/32b integer divider using the digit-recurrence division method and the on-the-fly conversion algorithm, is presented. A fast normaliser is used as the preprocessor of the proposed integer divider. To reduce maximum division time, the proposed divider uses radix-4/2 division, instead of the traditional radix-2 division. On-the-fly quotient adjustment is also realised in the convert... View full abstract»

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  • Fault-tolerant gamma interconnection networks by chaining

    Publication Year: 2000, Page(s):75 - 81
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (356 KB)

    The authors propose two single-fault-tolerant gamma interconnection networks. The first is a partially chained gamma interconnection network (PCGIN) with two disjoint paths between any source-destination pair. A PCGIN has the characteristics of one fault tolerance and destination tag routing, but backtracking may be necessary when a fault occurs. To eliminate the backtracking penalties of a PCGIN,... View full abstract»

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  • Decoding of CISC instructions in superscalar processors with high issue rate

    Publication Year: 2000, Page(s):101 - 107
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (328 KB)

    The paper examines the design issues of decoders, including the primitive operation (POP) translation strategies and the decoding rules, for CISC superscalar processors to exploit a higher degree of parallel execution. Attention is focused on the x86 instruction set because of its popularity. There are two different approaches regarding POP translation strategies: one is to merge the address gener... View full abstract»

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  • Time-redundant recovery policy of TMR failures using rollback and roll-forward methods

    Publication Year: 2000, Page(s):124 - 132
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (424 KB)

    A time-redundant approach is proposed by adopting a rollback and/or roll-forward technique to recover TMR failures producing incorrect majority outputs in a TMR (structured) system that uses the simplest spatial redundancy. This technique is apparently effective in recovering TMR failures primarily caused by transient faults. The proposed policies carry out fewer reconfigurations at the cost of (m... View full abstract»

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  • Three alternative architectures of digital ratioed compressor design with application to inner-product processing

    Publication Year: 2000, Page(s):65 - 74
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (548 KB)

    Inner-product calculations are often required in digital neural computing. The critical path of the inner product of two binary vectors is the carry propagation delay generated from individual product terms. Three alternative architecture for arranging digital ratioed compressors are presented, to reduce the carry propagation delay in the critical path wherein an improved design of a 3-2 compresso... View full abstract»

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  • Multi-level logic optimisation based on permissible perturbations

    Publication Year: 2000, Page(s):53 - 58
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (284 KB)

    The concept of permissible logic perturbations is introduced as a method for logic optimisation of multi-level digital circuits. The presented approach, denoted as a wave synthesis, refers to a sequence of procedures performed in order of logic levels that transform a perturbation region of multi-input, multi-output wires into a multi-input, multi-output logic subcircuit. The primary goal of the w... View full abstract»

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  • Completion-detecting carry select addition

    Publication Year: 2000, Page(s):93 - 100
    Cited by:  Papers (6)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (444 KB)

    Logic analysis, circuit implementation and verification of a novel self-timed adder scheme based on carry select (CS) logic are presented. The preliminary analysis of the variable-time behaviour of CS logic justifies the design of self-timed CS adders, and identifies the best choice for the block size to optimise the average performance. The logic design and full-custom circuit implementation is d... View full abstract»

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  • Performance analysis of VLIW compilation techniques

    Publication Year: 2000, Page(s):117 - 123
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (460 KB)

    VLIW machines derive their performance advantage from the parallel execution of independent instructions that have been scheduled by the compiler. The paper evaluates the performance impact of a set of important VLIW compilation techniques on non-numerical integer programs. In particular, several key scheduling approaches, including software pipelining versus loop unrolling, DAG-based versus trace... View full abstract»

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  • Heuristics in the routing algorithm for circuit layout design

    Publication Year: 2000, Page(s):59 - 64
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (332 KB)

    New heuristics in solving the maze routing problem are presented. The proposed MQ algorithm generates a shortest path based on the depth-first vertex traversal approach in the direction towards the target. A set of heuristics is formulated by assigning a directional priority sequence to each vertex while finding the path. This method will find a shortest path between two points, if one exists, on ... View full abstract»

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