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IEE Proceedings E - Computers and Digital Techniques

Issue 3 • Date May 1990

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Displaying Results 1 - 7 of 7
  • High-throughput, reduced hardware systolic solution to prime factor discrete Fourier transform algorithm

    Publication Year: 1990, Page(s):191 - 196
    Cited by:  Papers (13)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (492 KB)

    The paper discusses a novel systolic implementation of the row-column method for solving the prime factor discrete Fourier transform (DFT) algorithm. It deals, in particular, with the two-factor decomposition where the transform length N is an odd multiple of 4. By processing the four-point row-DFTs coefficient by coefficient, rather than DFT by DFT, as is conventionally done, it is seen how pipel... View full abstract»

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  • Decoding the (24,12,8) Golay code

    Publication Year: 1990, Page(s):202 - 206
    Cited by:  Papers (28)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (344 KB)

    A simplified procedure, called the shift-search method, is developed to decode the three possible errors in a (23,12,7) Golay codeword. The algebraic decoding algorithm developed recently by Elia is compared with this algorithm. A computer simulation shows that both algorithms are modular, regular and naturally suitable for either VLSI or software implementation. Both of these algorithms decode ef... View full abstract»

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  • Detecting edges in an image using powers-of-two coefficients

    Publication Year: 1990, Page(s):185 - 190
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (764 KB)

    The process of detecting edges in an image includes the convolution of the image with an operator or template, whose coefficients are determined by the algorithm in use. By approximating these coefficients to the nearest power-of-two, the convolution operation is greatly speeded up, since each multiplication can instead be performed by a shift operation. This is attractive both for a software as w... View full abstract»

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  • Channel codec performs versatile error-correction

    Publication Year: 1990, Page(s):197 - 201
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (408 KB)

    A proposal of a flexible error-correcting codec for data transmission is presented. The field of possible applications is explained. The flexible codec allows implementation of RS and binary BCH codes with variable parameters within the same device. In the future the progress in VLSI technology will permit integration as a flexible one chip channel codec. View full abstract»

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  • Implementation of a mask verification language and its compiler

    Publication Year: 1990, Page(s):207 - 217
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (860 KB)

    The paper describes the design and philosophy of a mask verification language (MVL) and its compiler. Mask verification tools have to be programmable, because of the large software investment they require, and the speed at which fabrication technology changes. The language described allows a designer to specify the topological structure of a device (the device description), and to attach to it a p... View full abstract»

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  • Bipartite distance-regular interconnection topology for fault-tolerant multiprocessor systems

    Publication Year: 1990, Page(s):173 - 184
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1028 KB)

    The authors propose a bipartite, distance-regular topology for interconnection networks to build large multiprocessor systems. The connectivity for these networks is the best possible and their average internodal distance is roughly equal to half the diameter. These features show that the proposed networks have relatively high densities, and are capable of maximal fault-tolerance. The topology all... View full abstract»

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  • Redundancy design for a fault tolerant systolic array

    Publication Year: 1990, Page(s):218 - 226
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (680 KB)

    A systematic design methodology for redundant systolic arrays is proposed. Redundancies consisting of space-shift, time-shift and space-time-shift schemes are applied successfully to detect or mask permanent faults, transient faults or both. Various redundancy designs for different utilisation efficiencies of processor elements can be obtained at the design stage by a dependent graph and its assoc... View full abstract»

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