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Solid-State Circuits, IEEE Journal of

Issue 7 • Date July 2000

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Displaying Results 1 - 21 of 21
  • Editorial

    Publication Year: 2000 , Page(s): 926 - 927
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    Freely Available from IEEE
  • New associate editor [Editor]

    Publication Year: 2000 , Page(s): 928
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    Freely Available from IEEE
  • Guest Editorial

    Publication Year: 2000 , Page(s): 929 - 931
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    Freely Available from IEEE
  • A high-dynamic-range CMOS image sensor for automotive applications

    Publication Year: 2000 , Page(s): 932 - 938
    Cited by:  Papers (40)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (419 KB)  

    In this paper, a 256/spl times/256 pixel CMOS imager is described that exhibits 120 dB dynamic range, 56 dB signal-to-noise ratio (SNR), 65% fill factor, and an effective frame rate of 50 Hz. This has been achieved using a unique combination of a multiexposure and a multigain linear readout. The imager has been integrated in 1 /spl mu/m double-metal CMOS technology. The intended application is for driver's assistant systems, but the imager can be used for a wide range of applications requiring high dynamic range. View full abstract»

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  • Vertically integrated sensors for advanced imaging applications

    Publication Year: 2000 , Page(s): 939 - 945
    Cited by:  Papers (11)  |  Patents (1)
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    A thin film on ASIC (TFA) image sensor is fabricated depositing an amorphous silicon thin-film detector onto a CMOS ASIC. With regards to advanced imaging systems, TFA provides enhanced performance and more flexibility than conventional technologies. Extensive on-chip signal processing is feasible, as well as small pixels for high resolution imagers. Two new TFA imager prototypes have recently been fabricated. High-resolution image sensor (HIRISE II) with 1024/spl times/128 pixels is an active pixel sensor suited for digital photography. Local autoadaptiver sensor (LARS II) with 368/spl times/256 pixels splits the illumination information into two signals, thereby providing a dynamic range of more than 120 dB, as required by automotive applications. Both prototypes include correlated double sampling and double delta sampling for efficient suppression of fixed pattern noise. View full abstract»

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  • A 1.3-GOPS parallel DSP for high-performance image-processing applications

    Publication Year: 2000 , Page(s): 946 - 952
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    A programmable digital signal processor (DSP) for real-time image processing is presented that combines the concepts of single-instruction multiple-data (SIMD) and very long instruction word with a high utilization of parallel resources on instruction and data level. The SIMD approach has been extended with autonomous instruction selection capabilities (ASIMD), which offers to control four parallel datapaths with low area overhead. The memory concept is adapted to image-processing requirements and follows two basic rules: shared data have to be accessed regularly in the shape of a matrix and are stored in the matrix memory. As soon as data are accessed irregularly, they are stored in the private cache memories. The matrix memory allows parallel, conflict-free access from all datapaths in a single clock cycle. The DSP achieves 1.3-GOPS performance at 66 MHz. A first prototype in 0.5-/spl mu/m CMOS technology has been fabricated. View full abstract»

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  • Asynchronous 250-Mb/s optical receivers with integrated detector in standard CMOS technology for optocoupler applications

    Publication Year: 2000 , Page(s): 953 - 958
    Cited by:  Papers (27)  |  Patents (10)
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    A high-speed ten-channel optical receiver, integrated in a standard 0.6-/spl mu/m CMOS technology, is presented. Each data channel consists of a spatially modulated light detector (SML-detector) and a low-offset receiver. The SML detector has a much higher intrinsic bandwidth than a conventional photodiode junction implemented in standard CMOS. One channel of the ten is sacrificed and used as a reference to define the threshold level for the other channels. The optical receiver can handle up to 250 Mb/s of noncoded data (including dc) per channel at 20 /spl mu/W average light input power (/spl lambda/=860 nm). Power dissipation per channel is only 4 mW. When combined with appropriate light emitters, a compact and low-cost optocoupler can be obtained with improved speed performance compared to existing optocouplers. View full abstract»

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  • A 200-MHz IF 11-bit fourth-order bandpass /spl Delta//spl Sigma/ ADC in SiGe

    Publication Year: 2000 , Page(s): 959 - 967
    Cited by:  Papers (16)  |  Patents (1)
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    This paper demonstrates the design of an integrated fourth-order bandpass sigma-delta converter, which is capable of digitizing a 200-kHz band at 200 MHz with 11-bit accuracy. The converter has been successfully fabricated in a 50-GHz SiGe bipolar technology, and the modulator consumes 21 mA at 3 V. The converter is aimed at the digitization of wireless signals at a high first intermediate frequency with a wide dynamic range. View full abstract»

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  • 14-bit 2.2-MS/s sigma-delta ADC's

    Publication Year: 2000 , Page(s): 968 - 976
    Cited by:  Papers (13)
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    This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 /spl mu/m CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections. View full abstract»

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  • A 200-MHz sub-mA RF front end for wireless hearing aid applications

    Publication Year: 2000 , Page(s): 977 - 986
    Cited by:  Papers (3)  |  Patents (1)
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    A hearing-aid system with RF connection between both ear-pieces is described and its transceiver is introduced. A suitable 200-MHz RF front end has been implemented in a 0.8-/spl mu/m BiCMOS technology. Low power consumption and area constraint were key requirements. The chip comprises a low noise amplifier (LNA), a single balanced mixer, a varactor tuned LC local oscillator with buffer and a 16/17 dual-modulus prescaler. The LNA has a measured gain of 17.5 dB at 200 MHz. The conversion g/sub m/ of the mixer is 1.88 mS. The overall voltage gain and noise figure are 26 dB and 5.2 dB, respectively. The voltage-controlled oscillator's (VCO's) phase noise is -104.7 dBc/Hz at an offset of 24 kHz. View full abstract»

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  • A 200-MHz IF BiCMOS signal component separator for linear LINC transmitters

    Publication Year: 2000 , Page(s): 987 - 993
    Cited by:  Papers (13)  |  Patents (55)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (131 KB)  

    The linear amplification with nonlinear components (LINC) transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. The signal component separator (SCS) is a crucial signal processing function of LINC. It forms two constant-amplitude phase-modulated signal components from the input signal. Due to the nonlinear signal processing involved, digital signal processing (DSP) implementation of the SCS at baseband has so far been assumed to be the best choice although it suffers from matching, bandwidth and power consumption problems. In this paper a new SCS architecture based on analog integrated circuit techniques is presented to avoid the disadvantages in a DSP based realization. A 200-MHz IF SCS chip using the proposed architecture was designed and fabricated in a 0.8 /spl mu/m BiCMOS process. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that spurious levels around -50 dBc could be obtained with a /spl pi//4-shifted DQPSK modulated North American Digital Cellular (NADC) signal. This implies a high degree of linearity in the implemented LINC transmitter. View full abstract»

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  • Reducing MOSFET 1/f noise and power consumption by switched biasing

    Publication Year: 2000 , Page(s): 994 - 1001
    Cited by:  Papers (93)  |  Patents (13)
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    Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 /spl mu/m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%. View full abstract»

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  • Analysis and experimental verification of digital substrate noise generation for epi-type substrates

    Publication Year: 2000 , Page(s): 1002 - 1008
    Cited by:  Papers (64)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    Substrate coupling in mixed-signal IC's can cause important performance degradation of the analog circuits. Accurate simulation is therefore needed to investigate the generation, propagation, and impact of substrate noise. Recent studies were limited to the time-domain behavior of generated substrate noise and to noise injection from a single noise source. This paper focuses on substrate noise generation by digital circuits and on the spectral content of this noise. To simulate the noise generation, a SPICE substrate model for heavily doped epi-type substrates has been used. The accuracy of this model has been verified with measurements of substrate noise, using a wide-band, continuous-time substrate noise sensor, which allows accurate measurement of the spectral content of substrate noise. The substrate noise generation of digital circuits is analyzed, both in the time and frequency domain, and the influence of the different substrate noise coupling mechanisms is demonstrated. It is shown that substrate noise voltages up to 20 mV are generated and that, in the frequency band up to 1 GHz, noise peaks are generated at multiples of the clock and repetition frequency. These noise signals will strongly deteriorate the behavior of small signal analog amplifiers, as used in integrated front-ends. View full abstract»

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  • Dual-threshold voltage techniques for low-power digital circuits

    Publication Year: 2000 , Page(s): 1009 - 1018
    Cited by:  Papers (123)  |  Patents (35)
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    Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented. A dual-V/sub t/ domino logic style that provides the performance equivalent of a purely low-V/sub t/ design with the standby leakage characteristic of a purely high-V/sub t/ implementation is also proposed. View full abstract»

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  • A 5.3-GHz programmable divider for HiPerLAN in 0.25-/spl mu/m CMOS

    Publication Year: 2000 , Page(s): 1019 - 1024
    Cited by:  Papers (41)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (173 KB)  

    A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D-flip-flop (DFF). An improved glitch-free phase switching architecture through the use of retimed multiplexer control signals is introduced. A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25-/spl mu/m technology occupies 0.09 mm/sup 2/; it consumes 17.4 mA at 1.8 V and 26.8 mA at 2.2 V. Operation of 5.5 GHz with 300-mV/sub pk/ single-ended input is achieved with a 2.2-V supply. The residual phase noise at the output is -131 dBc/Hz at an offset of 1 kHz from the carrier while operating from a 5.5 GHz input. View full abstract»

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  • 2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing

    Publication Year: 2000 , Page(s): 1025 - 1033
    Cited by:  Papers (15)  |  Patents (5)
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    A vector unit for high-performance three-dimensional graphics computing has been developed. We implement four floating-point multiply-accumulate units, which execute multiply-add operations with one throughput; one floating-point divide/square root unit, which executes division and square-root operations with six cycles at 300 MHz; and one vector general-purpose register file, which has 128 bits/spl times/32 words. The parallel execution of all units delivers a peak performance of 2.44 GFLOPS at 300 MHz. View full abstract»

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  • A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization

    Publication Year: 2000 , Page(s): 1034 - 1038
    Cited by:  Papers (64)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (115 KB)  

    A fully integrated 2-GHz very low-phase-noise LC-tank voltage-controlled oscillator (VCO) set with flicker noise upconversion minimization is presented. Using only integrated planar inductors, the measured phase noise is as low as -125.1 dBc/Hz at 600-kHz offset and -138 dBc/Hz at 3 MHz. The excellent phase-noise performance is achieved by means of an in-house-developed integrated inductor simulator optimizer. To minimize the upconversion of flicker noise to 1/f/sup 3/ phase noise, a flicker-noise upconversion factor is defined, which can easily be extracted from circuit simulation. The technique is applied to demonstrate the relationship between the flicker-noise upconversion and the overdrive level of the oscillators' MOS cross-coupled pair and to develop circuit balancing techniques to even further reduce the flicker-noise upconversion. The 1/f/sup 3/ phase-noise corner is minimized to be less than 15 kHz. The VCO's are implemented in a three-metal layer, 0.65-/spl mu/m BiCMOS process, using only MOS active devices. View full abstract»

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  • A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology

    Publication Year: 2000 , Page(s): 1039 - 1045
    Cited by:  Papers (139)  |  Patents (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (147 KB)  

    A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 /spl mu/m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider. View full abstract»

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  • Low-power BiCMOS op-amp with integrated current-mode charge pump

    Publication Year: 2000 , Page(s): 1046 - 1050
    Cited by:  Papers (11)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (113 KB)  

    An operational amplifier with an integrated current-mode charge pump is presented. This operational amplifier functions with a 4-/spl mu/A single-supply above-the-rail input and rail-to-rail output. Having an integrated charge pump greatly simplifies the amplifier design while providing an increased dynamic range over other rail-to-rail amplifiers. The current-mode charge pump limits the power loss associated with feedthrough current found in most voltage mode designs. The resulting amplifier, designed with a dual-well BiCMOS process, achieves a bandwidth of 54 kHz while consuming less than 10 /spl mu/W. View full abstract»

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  • Investigation on low-voltage low-power silicon bipolar design topology for high-speed digital circuits

    Publication Year: 2000 , Page(s): 1051 - 1054
    Cited by:  Papers (8)
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    This paper investigates a bipolar design topology which is suitable to operate from a voltage supply well below 1.5 V, while maintaining the ability of high frequency operation. The topology has been applied in the design of different divide-by-4 circuits, utilizing a 20-GHz 0.6-/spl mu/m Si bipolar technology. The different versions featured slight modifications in the architecture of the logic cells and the influence on the frequency and supply voltage range of operation has been investigated. Measurements have shown operation from 1.0-V supply voltage and up to 4.2-GHz input frequency to 1.5 V and up to 6 GHz. The power consumption is approximately 0.3 mW/latch and 1.2 mW/latch, respectively. View full abstract»

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  • A 256/spl times/256 pixel smart CMOS image sensor for line-based stereo vision applications

    Publication Year: 2000 , Page(s): 1055 - 1061
    Cited by:  Papers (13)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (237 KB)  

    This paper presents a 256/spl times/256 pixel smart CMOS image sensor for line based vision applications. By combining the edge-based analog processing technique with an active pixel array, a dense and fast on-chip analog image processing has been achieved. The on-chip processing unit includes (1) an analog histogram equalizer, (2) a programmable recursive Gaussian filter, (3) a spatio-temporal differentiator, and (4) a local extrema extractor. An electronic shutter is applied to the active pixel sensor array in order to adapt the exposure time as a function of global illumination. The on-chip histogram equalizer extends the image into a constant and optimal range for all the following processing operators and gives a stable and predictable precision of the analog processing. A prototype chip has been designed and fabricated in a standard 0.8-/spl mu/m CMOS process with double poly and double metal, giving a pixel pitch of 20 /spl mu/m and die size of 7/spl times/7 mm/sup 2/. A line processing time is compatible with TV line scan period. The worst case power consumption measures 40 mA at 5 V. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan