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Electron Devices, IEEE Transactions on

Issue 7 • Date Jul 2000

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Displaying Results 1 - 25 of 37
  • Performance of the floating gate/body tied NMOSFET photodetector on SOI substrate

    Publication Year: 2000 , Page(s): 1375 - 1384
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    In this paper, we report the performance of a new photodetector fabricated on SOI substrate using a standard CMOS process. The photodetector is formed by connecting the gate and the body of a NMOSFET. The gate-body terminal is left floating so that the potential can be modulated by illumination. The depletion region induced by the floating gate separates the optically generated electron-hole pairs in the direction perpendicular to the current. This increases the body potential and induces positive charges to the gate due to the tied gate and body. It results in a further turn on of the NMOSFET and extra optical current. The gain behavior under different illumination is characterized and explained by transistor theory. A wide signal range of more than six orders of magnitude and a high responsivity of about 1000 A/W have been obtained with an operating voltage as low as 0.2 V. The device scaling properties, noise behavior and transient response are also studied View full abstract»

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  • Sensitivity analysis of TWT's small signal gain based on the effect of rod shape and dimensions

    Publication Year: 2000 , Page(s): 1457 - 1462
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    An extensive study aiming at analyzing the effect of rod shapes and dimensions on the gain of helix traveling wave tubes (TWTs) is performed. The evaluation of tube small-signal gain is obtained by making use of a rigorous field analysis which takes into account the helix tape model and the dielectric inhomogeneous loading conditions. Computing time to perform the analysis is extremely low compared with the time required in the case of a full wave, three-dimensional (3-D) electromagnetic simulator. The accuracy of the simulation approach has been extensively verified in a previous paper. A novel expression for the attenuation constant has been introduced in the model to improve the quality of results. The proposed study allows a better understanding of tube behavior before fabrication highlighting the contribution of the shape, the mechanical tolerances and the εr variation of the rods to the small-signal gain View full abstract»

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  • Effect of vacuum ultraviolet radiation on the gap fill properties of Teflon amorphous fluoropolymer film deposited by direct liquid injection

    Publication Year: 2000 , Page(s): 1463 - 1465
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (80 KB)  

    In this work, the roles of vacuum ultraviolet (VUV) photons in improving the gap fill properties of a low dielectric constant (K) material (Teflon amorphous fluoropolymer, K=1.93) deposited by direct liquid injection assisted rapid photothermal chemical vapor deposition technique are discussed. A qualitative explanation is presented wherein it is proposed that high-energy photons provide photoexcitation of the species involved in the deposition of Teflon AFTM, thereby lowering the activation energy and migrational enthalpy required for surface diffusion leading to a higher molecular mobility on the patterned surface View full abstract»

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  • Dynamic performance of UV photodetectors based on polycrystalline diamond

    Publication Year: 2000 , Page(s): 1334 - 1340
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    Dynamic behavior of photogenerated carriers in diamond-based UV photodetectors is investigated over a wide excitation frequency range, enabling an analysis of the influence of film morphology and impurity content on device response times. Under pulsed light excitation, short time detector photoresponse varies from 2.5 to 10 ns, whereas carrier lifetimes estimated under steady-state illumination lie in the 0.1-1 ns range, exhibiting a small dependence on the film microstructure. Conversely, very long response times, strongly dependent on film characteristics, are detected by decreasing the excitation frequency. Such results are discussed in terms of carrier recombination at defect- and impurity-related centers, trapping at localized states close to the band edges, and dispersive transport. It is suggested that device response times are mainly related to charge trapping either into discrete or continuously distributed energy levels, rather than to recombination of carriers at midgap defect states View full abstract»

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  • Novel fabrication of Ti-Pt-Au/GaAs Schottky diodes

    Publication Year: 2000 , Page(s): 1465 - 1468
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    A novel fabrication process for evaporated refractory-metal/n-GaAs Schottky contacts is presented. This process avoids the use of photoresist lift-off in order to maintain an exceptionally clean Schottky interface. Resulting millimeter-wave varactor diodes exhibit the same anode quality as previous electroplated platinum/n-GaAs varactor diodes but with improved reliability, repeatability and cost. A titanium deposition-rate of 1.2-1.6 nm/s was found to yield minimum ideality factor and breakdown voltages equivalent to those of Pt devices at a doping density of 1×1017 cm-3. Devices fabricated on material doped at 2.3×1017 cm-3 and above, however, had significantly lower breakdown voltages compared to platinum diodes. This is believed to be due to the lower barrier height of the titanium anodes, which causes an increased tunneling current View full abstract»

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  • Compact modeling of high-frequency distortion in silicon integrated bipolar transistors

    Publication Year: 2000 , Page(s): 1529 - 1535
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    The high-frequency distortion behavior of integrated silicon bipolar transistors is investigated experimentally and theoretically. Single-tone measurements using an automated setup are performed on transistors with various sizes and of different type, that were fabricated in a state-of-the-art production process offering high-speed and high-voltage transistor versions. The measured data, which were taken on devices laid out in usual high-frequency test pads, are compared to the advanced compact model HICUM showing excellent agreement over input power, bias, and frequency. In addition, a simplified model is used together with a Volterra-series approach to identify the nonlinear effects that are most important at high frequencies View full abstract»

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  • A novel lateral bipolar transistor with 67 GHz fmax on thin-film SOI for RF analog applications

    Publication Year: 2000 , Page(s): 1536 - 1541
    Cited by:  Papers (23)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12×3.0 μm2, low base resistance of 270 Ω due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f max of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications View full abstract»

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  • Light dependence of SOI MOSFET with nonuniform doping profile

    Publication Year: 2000 , Page(s): 1469 - 1471
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    The light dependence of a fully depleted short channel silicon-on-insulator (SOI) MOSFET is investigated. As the photon flux density increases, there is a lowering in the surface potential barrier called the photon induced barrier lowering (PIBL). The threshold voltage shows a logarithmic reduction with the increase in the incident flux density. The drain source current and the transconductance significantly increase under the incident optical flux density. The device will be useful for high speed application in optical systems View full abstract»

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  • Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

    Publication Year: 2000 , Page(s): 1393 - 1400
    Cited by:  Papers (30)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (180 KB)  

    Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications View full abstract»

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  • Inverse modeling of two-dimensional MOSFET dopant profile via capacitance of the source/drain gated diode

    Publication Year: 2000 , Page(s): 1385 - 1392
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    This paper proposes and demonstrates a new approach to two-dimensional (2-D) dopant profile extraction for MOSFETs by treating the source/drain-to-substrate junction as a gated diode. The small-signal capacitance of the diode measured as a function of gate and source/drain bias is used as the target to be matched in an inverse modeling process. It is shown that this capacitance allows both the substrate dopant profile in the channel region and the source/drain-to-substrate profile parallel to the surface to be evaluated with a single set of measurement data. Experimental results for n-MOSFET's with drawn channel length =1 μm and 0.265 μm are presented. Comparison of other electrical measurement with simulation data based on the extracted profile is also given View full abstract»

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  • The influence of elevated temperature on degradation and lifetime prediction of thin silicon-dioxide films

    Publication Year: 2000 , Page(s): 1514 - 1521
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    The reliability of gate oxide is a crucial aspect of device downscaling. In this paper, we demonstrate that increasing operating temperature of downscaled logic devices combined with the increased detrimental effect of elevated temperature on very thin SiO2 films will significantly reduce the device reliability. We discuss the effect of elevated temperature on the factors contributing to oxide breakdown and observe that their combined effect does not result in Arrhenius-like decrease of time-to-breakdown. This is related to our observation that oxide defects created at different temperatures are not completely equivalent. Consequently, oxide damage created during electrical stress at different temperatures is not simply cumulative. We also discuss several possible microscopic models attempting to explain this observation. Finally, we briefly review the methodology of the oxide reliability prediction and present a reliability projection for very thin oxides at the expected elevated operating temperatures View full abstract»

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  • Plasma-induced charging damage in ultrathin (3-nm) gate oxides

    Publication Year: 2000 , Page(s): 1355 - 1360
    Cited by:  Papers (5)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    Plasma-induced damage in various 3-nm-thick gate oxides (i.e., pure oxides and N2O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Both charge-to-breakdown and gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as the wafer edge for pMOS devices, while only at the wafer center for nMOS devices. These interesting observations could be explained by the strong polarity dependence of ultra thin oxides in charge-to-breakdown measurements of nMOS devices. In addition, pMOS devices were found to be more susceptible to charging damage, which can be attributed to the intrinsic polarity dependence in tunneling current between nand p-MOSFETs. More importantly, our experimental results demonstrated that stress-induced leakage current (SILC) caused by plasma damage can be significantly suppressed in N2O-nitrided oxides, compared to pure oxides, especially for pMOS devices. Finally, nitrided oxides were also found to be more robust when subjected to high temperature stressing. Therefore, nitrided oxides appear to be very promising for reducing plasma charging damage in future ULSI technologies employing ultrathin gate oxides View full abstract»

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  • The performance and reliability of PMOSFET's with ultrathin silicon nitride/oxide stacked gate dielectrics with nitrided Si-SiO2 interfaces prepared by remote plasma enhanced CVD and post-deposition rapid thermal annealing

    Publication Year: 2000 , Page(s): 1361 - 1369
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si3N4 onto oxides. Compared to PMOSFET's with heavily doped p+-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys View full abstract»

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  • Low temperature analysis of 0.25 μm T-gate strained Si/Si0.55Ge0.45 n-MODFET's

    Publication Year: 2000 , Page(s): 1477 - 1483
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    A low temperature dc and HF investigation of 0.25 μm T-gate Si/Si0.55Ge0.45 n-MODFET's is presented. Outstanding maximum oscillation frequencies fmax range from 100-120 GHz at 300 K up to 195 GHz at 50 K. These high-frequency characteristics are the first reported at low temperature on Si/SiGe n-MODFET's and are also the highest room temperature data reported so far; physical modeling is used to explain the main trends observed when cooling down the n-MODFET. Many experimental data are presented. The dependence on temperature and biases of the important small-signal equivalent circuit parameters is investigated to analyze the device high-frequency performances and the minimum noise figure of the intrinsic device is determined View full abstract»

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  • Stress induced leakage current analysis via quantum yield experiments

    Publication Year: 2000 , Page(s): 1341 - 1348
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    This paper investigates the physical characteristics of stress induced leakage current (SILC) by means of quantum yield (QY) measurements and simulations. QY experiments allow us to infer the energy of tunneling electrons, which is an important factor for the damage generation process. The energy of SILC electrons is analyzed in three different types of p-MOSFET devices: n+ gate surface channel and buried channel, and p+ gate surface channel. We show that an extra tunneling current component due to native traps can be present even in virgin devices and it is elastic. Then it is shown that SILC electrons have less energy than direct tunneling electrons. This energy loss is then extracted from experimental data and the limitations of this extraction technique are addressed. Finally, experiments on p+ gate p-MOSFET clearly demonstrate that electrons tunneling through traps created by electrical stress lose energy irrespective of their initial band. It is then concluded that native and stress induced traps have different physical characteristics View full abstract»

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  • Time dependent breakdown of ultrathin gate oxide

    Publication Year: 2000 , Page(s): 1416 - 1420
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    Time dependent dielectric breakdown (TDDB) of ultrathin gate oxide (<40 Å) was measured for a wide range of oxide fields (3.4<|Eox|<10.3 MV/cm) at various temperatures (100⩽T⩽342°C). It was found that TDDB of ultrathin oxide follows the E model. It was also found that TDDB t50 starts deviating from the 1/E model for fields below 7.2 MV/cm. Below 4.8 MV/cm, TDDB t50 of intrinsic oxide increased above the value predicted by the E model obtained for fields >4.8 MV/cm. The TDDB activation energy for this type of gate oxide was found to have linear dependence on oxide field. In addition, we found that γ (the field acceleration parameter) decreases with increasing temperature. Furthermore, it was found that testing at high temperatures (up to 342°C) and low electric field values did not introduce new gate oxide failure mechanism. It is also shown that TDDB data obtained at very high temperature (342°C) and low fields can be used to generate TDDB model at lower temperatures and low fields. Our results (an enthalpy of activation of 1.98 eV and dipole moment of 12.3 eÅ) are in complete agreement with previous results by McPherson and Mogul. Additionally, it was found that TDDB is exponentially dependent on the gate voltage View full abstract»

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  • Accurate contact resistivity extraction on Kelvin structures with upper and lower resistive layers

    Publication Year: 2000 , Page(s): 1431 - 1439
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    An accurate procedure to extract contact resistivity from contact resistance measurements made on both D-resistor and L-resistor type Kelvin cross test structures with both upper and lower resistive layers is presented. Through computer simulation it can be shown that the collar effects of both upper and lower layers are additive when both layers have a symmetric geometry. The method is based on the determination of a set of “universal curves” through computer simulation. Using dimensionless variables, these curves can be employed in all experimental conditions, eliminating the need of further simulations View full abstract»

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  • Theory and small signal analysis for a new bipolar injection transit time device (BIPOLITT)

    Publication Year: 2000 , Page(s): 1310 - 1314
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB)  

    We have proposed and analyzed a new millimeter and submillimeter wave transit time device, the bipolar injection and transit time diode (BIPOLITT). The theory and small signal analysis for a two-terminal type rf operation is presented here. The device structure is similar to a heterojunction bipolar transistor (HBT) with an rf floating base. The relatively longer base is utilized to achieve an injection-phase delay close to 180°. The collector depletion region is used as drift region. As an example, a BIPOLITT diode for 300-400 GHz operation is designed, and its small signal specific negative resistance is calculated to be about -3×10-7 Ω·cm2 View full abstract»

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  • 40% efficient thin-film surface-textured light-emitting diodes by optimization of natural lithography

    Publication Year: 2000 , Page(s): 1492 - 1498
    Cited by:  Papers (56)  |  Patents (37)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    In conventional light-emitting diodes (LEDs), the external efficiency is limited by total internal reflection at the semiconductor-air interface. The problem can be overcome by the concept of the nonresonant cavity LED, which is an LED with a textured top surface and a rear reflector. The surface is textured using natural lithography. A monolayer of randomly positioned polystyrene spheres acts as a mask for dry etching. We present details about the optimization of the parameters of the texturing process for GaAs/AlGaAs LEDs. The studied parameters are the size of the spheres, the distribution of the spheres on the surface and the etching depth. Using optimized texturing conditions, we have realized un-encapsulated top-emitting oxide-confined GaAs/AlGaAs nonresonant cavity LEDs with an external quantum efficiency of 40% View full abstract»

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  • Highly robust ultrathin silicon nitride films grown at low-temperature by microwave-excitation high-density plasma for giga scale integration

    Publication Year: 2000 , Page(s): 1370 - 1374
    Cited by:  Papers (15)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    This paper focuses attention on electrical properties of ultra-thin silicon nitride films grown by radial line slot antenna high-density plasma system at a temperature of 400°C as an advanced gate dielectric film. The results show low density of interface trap and bulk charge, lower leakage current than jet vapor deposition silicon nitride and thermally grown silicon oxide with same equivalent oxide thickness. Furthermore, they represent high breakdown field intensity, almost no stress-induced leakage current, very little trap generation even in high-field stress, and excellent resistance to boron penetration and oxidation View full abstract»

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  • The red shift of ZnSSe metal-semiconductor-metal light emitting diodes with high injection currents

    Publication Year: 2000 , Page(s): 1330 - 1333
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (64 KB)  

    The reliable n+-ZnSSe metal-semiconductor-metal (MSM) blue-green light emitting diodes (LED's) have been fabricated. The contact metal was CuGe/Pt/Au. The current transport mechanisms agree very well with the back to back tunneling diodes. The kink phenomena were observed in the MSM current-voltage curves. In the metal-semiconductor interface, the element Zn in ZnSSe can be replaced by Cu results in some acceptor levels as radiative recombination centers in the MS interface. The peak wavelength in the LED electroluminescent (EL) spectra was strongly dependent on the injection currents from 5 to 40 mA. The peak wavelength and full width at half maximum are 510 and 10 nm, respectively, at 10 mA injection current. When the injection current increases to 15 mA, the peak wavelength shifted to 530 nm due to different recombination centers. Further increasing the injection currents, the peak wavelength shifted slightly to the long wavelength side View full abstract»

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  • A 0.13 μm poly-SiGe gate CMOS technology for low-voltage mixed-signal applications

    Publication Year: 2000 , Page(s): 1507 - 1513
    Cited by:  Papers (4)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in detail to illustrate that it satisfies the requirements for mixed digital-analog circuitry. The use of asymmetric source/drain lateral profiles proves to be especially beneficial to analog applications View full abstract»

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  • Fracture strength and fatigue of polysilicon determined by a novel thermal actuator [MEMS]

    Publication Year: 2000 , Page(s): 1522 - 1528
    Cited by:  Papers (39)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    A novel thermal actuator for the determination of polysilicon fracture strength and investigation of its fatigue is presented. The actuator consists of two narrow beams, which expand due to electrical heating, and a cold plate to which a short fracture beam is attached. Because of its small dimensions, the actuator can be used for on-wafer testing. This method is suitable for tensile and compressive material. Using different types of fracture beams fracture strengths were compared for uniaxial tension and bending test. Using Weibull statistics, the fracture strength for polysilicon has been found to be (2.9±0.5) GPa in tensile tests and (3.4±0.5) GPa in bending tests. In fatigue investigations, we observe that fracture strength decreases slowly with time to 2.2 GPa after 106 cycles View full abstract»

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  • High-sensitivity photodetectors with on-chip pinhole for laser scanning microscopy

    Publication Year: 2000 , Page(s): 1472 - 1476
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    We manufactured new high-sensitivity solid-state detectors, specifically designed for measurements in laser scanning microscopy (LSM). These single-photon avalanche diodes (SPAD's) improve the performance achievable with an LSM apparatus in the optical inspection of microelectronic devices and circuits. Innovative detector structures that incorporate an on-chip pinhole filter are presented. Experimental measurements show that SPAD's perform better than standard photomultiplier tubes View full abstract»

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  • Fabrication and analysis of deep submicron strained-Si n-MOSFET's

    Publication Year: 2000 , Page(s): 1406 - 1415
    Cited by:  Papers (181)  |  Patents (150)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si0.8Ge0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego