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Electron Devices, IEEE Transactions on

Issue 7 • Date Jul 2000

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Displaying Results 1 - 25 of 37
  • The performance and reliability of PMOSFET's with ultrathin silicon nitride/oxide stacked gate dielectrics with nitrided Si-SiO2 interfaces prepared by remote plasma enhanced CVD and post-deposition rapid thermal annealing

    Page(s): 1361 - 1369
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    Ultrathin (~1.9 nm) nitride/oxide (N/O) dual layer gate dielectrics have been prepared by the remote plasma enhanced chemical vapor deposition (RPECVD) of Si3N4 onto oxides. Compared to PMOSFET's with heavily doped p+-poly-Si gates and oxide dielectrics, devices incorporating the RPECVD stacked nitrides display reduced tunneling current, effectively no boron penetration and improved interface characteristics. By preventing boron penetration into the bulk oxide and channel region, gate dielectric reliability and short channel effects are significantly improved. The hole mobility in devices with N/O dielectrics with equivalent oxide thickness between 1.8 nm and 3.0 nm is not significantly degraded. Because nitrogen is transported to the substrate/dielectric interface during post-deposition annealing, degradation of mobility during hot carrier stressing is significantly reduced for N/O devices. Compared with oxide, the tunneling current for N/O films with ~1.9 nm equivalent oxide thickness is lower by about an order of magnitude due to the larger physical thickness. Suppression of boron transport in nitride layers is explained by a percolation model in which boron transport is blocked in sufficiently thick nitrides, and is proportional to the oxide fraction in oxynitride alloys View full abstract»

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  • High-sensitivity photodetectors with on-chip pinhole for laser scanning microscopy

    Page(s): 1472 - 1476
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    We manufactured new high-sensitivity solid-state detectors, specifically designed for measurements in laser scanning microscopy (LSM). These single-photon avalanche diodes (SPAD's) improve the performance achievable with an LSM apparatus in the optical inspection of microelectronic devices and circuits. Innovative detector structures that incorporate an on-chip pinhole filter are presented. Experimental measurements show that SPAD's perform better than standard photomultiplier tubes View full abstract»

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  • Dynamic performance of UV photodetectors based on polycrystalline diamond

    Page(s): 1334 - 1340
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    Dynamic behavior of photogenerated carriers in diamond-based UV photodetectors is investigated over a wide excitation frequency range, enabling an analysis of the influence of film morphology and impurity content on device response times. Under pulsed light excitation, short time detector photoresponse varies from 2.5 to 10 ns, whereas carrier lifetimes estimated under steady-state illumination lie in the 0.1-1 ns range, exhibiting a small dependence on the film microstructure. Conversely, very long response times, strongly dependent on film characteristics, are detected by decreasing the excitation frequency. Such results are discussed in terms of carrier recombination at defect- and impurity-related centers, trapping at localized states close to the band edges, and dispersive transport. It is suggested that device response times are mainly related to charge trapping either into discrete or continuously distributed energy levels, rather than to recombination of carriers at midgap defect states View full abstract»

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  • Highly robust ultrathin silicon nitride films grown at low-temperature by microwave-excitation high-density plasma for giga scale integration

    Page(s): 1370 - 1374
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    This paper focuses attention on electrical properties of ultra-thin silicon nitride films grown by radial line slot antenna high-density plasma system at a temperature of 400°C as an advanced gate dielectric film. The results show low density of interface trap and bulk charge, lower leakage current than jet vapor deposition silicon nitride and thermally grown silicon oxide with same equivalent oxide thickness. Furthermore, they represent high breakdown field intensity, almost no stress-induced leakage current, very little trap generation even in high-field stress, and excellent resistance to boron penetration and oxidation View full abstract»

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  • Accurate contact resistivity extraction on Kelvin structures with upper and lower resistive layers

    Page(s): 1431 - 1439
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    An accurate procedure to extract contact resistivity from contact resistance measurements made on both D-resistor and L-resistor type Kelvin cross test structures with both upper and lower resistive layers is presented. Through computer simulation it can be shown that the collar effects of both upper and lower layers are additive when both layers have a symmetric geometry. The method is based on the determination of a set of “universal curves” through computer simulation. Using dimensionless variables, these curves can be employed in all experimental conditions, eliminating the need of further simulations View full abstract»

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  • Low temperature analysis of 0.25 μm T-gate strained Si/Si0.55Ge0.45 n-MODFET's

    Page(s): 1477 - 1483
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    A low temperature dc and HF investigation of 0.25 μm T-gate Si/Si0.55Ge0.45 n-MODFET's is presented. Outstanding maximum oscillation frequencies fmax range from 100-120 GHz at 300 K up to 195 GHz at 50 K. These high-frequency characteristics are the first reported at low temperature on Si/SiGe n-MODFET's and are also the highest room temperature data reported so far; physical modeling is used to explain the main trends observed when cooling down the n-MODFET. Many experimental data are presented. The dependence on temperature and biases of the important small-signal equivalent circuit parameters is investigated to analyze the device high-frequency performances and the minimum noise figure of the intrinsic device is determined View full abstract»

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  • A novel lateral bipolar transistor with 67 GHz fmax on thin-film SOI for RF analog applications

    Page(s): 1536 - 1541
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    In this paper, a novel lateral bipolar transistor on thin film silicon-on-insulator (SOI) is presented. With a small emitter size of 0.12×3.0 μm2, low base resistance of 270 Ω due to a novel Co silicided base electrode and low base-collector parasitic capacitances of 1.4 fF due to SOI material, it achieves the highest f max of 67 GHz among SOI bipolar transistors. Also, the low emitter-base capacitance of 1.5 fF and the low collector-substrate capacitance of 2.5 fF are realized. The transistor has a simple structure, which is fabricated with simplified processes without any new sophisticated technologies, excluding trench isolation and epitaxial base used in current bipolar transistors. This can lower the fabrication cost of transistors. We have demonstrated the possibility of lateral bipolar transistor on thin film SOI as next-generation device for RF analog applications View full abstract»

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  • Time dependent breakdown of ultrathin gate oxide

    Page(s): 1416 - 1420
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    Time dependent dielectric breakdown (TDDB) of ultrathin gate oxide (<40 Å) was measured for a wide range of oxide fields (3.4<|Eox|<10.3 MV/cm) at various temperatures (100⩽T⩽342°C). It was found that TDDB of ultrathin oxide follows the E model. It was also found that TDDB t50 starts deviating from the 1/E model for fields below 7.2 MV/cm. Below 4.8 MV/cm, TDDB t50 of intrinsic oxide increased above the value predicted by the E model obtained for fields >4.8 MV/cm. The TDDB activation energy for this type of gate oxide was found to have linear dependence on oxide field. In addition, we found that γ (the field acceleration parameter) decreases with increasing temperature. Furthermore, it was found that testing at high temperatures (up to 342°C) and low electric field values did not introduce new gate oxide failure mechanism. It is also shown that TDDB data obtained at very high temperature (342°C) and low fields can be used to generate TDDB model at lower temperatures and low fields. Our results (an enthalpy of activation of 1.98 eV and dipole moment of 12.3 eÅ) are in complete agreement with previous results by McPherson and Mogul. Additionally, it was found that TDDB is exponentially dependent on the gate voltage View full abstract»

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  • Sensitivity analysis of TWT's small signal gain based on the effect of rod shape and dimensions

    Page(s): 1457 - 1462
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    An extensive study aiming at analyzing the effect of rod shapes and dimensions on the gain of helix traveling wave tubes (TWTs) is performed. The evaluation of tube small-signal gain is obtained by making use of a rigorous field analysis which takes into account the helix tape model and the dielectric inhomogeneous loading conditions. Computing time to perform the analysis is extremely low compared with the time required in the case of a full wave, three-dimensional (3-D) electromagnetic simulator. The accuracy of the simulation approach has been extensively verified in a previous paper. A novel expression for the attenuation constant has been introduced in the model to improve the quality of results. The proposed study allows a better understanding of tube behavior before fabrication highlighting the contribution of the shape, the mechanical tolerances and the εr variation of the rods to the small-signal gain View full abstract»

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  • Inverse modeling of two-dimensional MOSFET dopant profile via capacitance of the source/drain gated diode

    Page(s): 1385 - 1392
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    This paper proposes and demonstrates a new approach to two-dimensional (2-D) dopant profile extraction for MOSFETs by treating the source/drain-to-substrate junction as a gated diode. The small-signal capacitance of the diode measured as a function of gate and source/drain bias is used as the target to be matched in an inverse modeling process. It is shown that this capacitance allows both the substrate dopant profile in the channel region and the source/drain-to-substrate profile parallel to the surface to be evaluated with a single set of measurement data. Experimental results for n-MOSFET's with drawn channel length =1 μm and 0.265 μm are presented. Comparison of other electrical measurement with simulation data based on the extracted profile is also given View full abstract»

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  • Hot electron and hot hole degradation of UHV/CVD SiGe HBT's

    Page(s): 1440 - 1448
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    We investigate the degradation in current gain and low-frequency noise of SiGe HBT's under reverse emitter-base stress due to hot electrons (forward-collector stress) and hot holes (open-collector stress). Contrary to previous assumptions we show that hot electrons and hot holes with the same kinetic energy generate different amounts of traps and hence have a different impact on device degradation. These results suggest that the accuracy of using forward-collector stress as an acceleration tool and reliability predictor must be carefully examined. We also present, for the first time, the effect of Ge profile shape on the reliability of SiGe HBT's, as well as discuss measurements on SiGe HBT's as a function of device geometry and temperature View full abstract»

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  • GaN n- and p-type Schottky diodes: Effect of dry etch damage

    Page(s): 1320 - 1324
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    The reverse breakdown voltage (VB) and forward turn-on voltage (VF) of n- and p-GaN Schottky diodes were used to examine the effects of Cl2/Ar and Ar plasma damage. Even short plasma exposures (4 secs) produced large changes in both VB and VF, with ion mass being a critical factor in determining the magnitude of the changes. The damage depth was established to be 500-600 Å and the damaged material could be removed in boiling NaOH solutions, producing a full recovery of the diode properties. Annealing at 700 to 800°C under N2 produced only a partial recovery of VB and VF View full abstract»

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  • Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime

    Page(s): 1349 - 1354
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    In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n+ poly-SiO2-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 Å have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 Å over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 Å for thickness 31-47 Å. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 Å over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 Å) View full abstract»

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  • Plasma-induced charging damage in ultrathin (3-nm) gate oxides

    Page(s): 1355 - 1360
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    Plasma-induced damage in various 3-nm-thick gate oxides (i.e., pure oxides and N2O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Both charge-to-breakdown and gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as the wafer edge for pMOS devices, while only at the wafer center for nMOS devices. These interesting observations could be explained by the strong polarity dependence of ultra thin oxides in charge-to-breakdown measurements of nMOS devices. In addition, pMOS devices were found to be more susceptible to charging damage, which can be attributed to the intrinsic polarity dependence in tunneling current between nand p-MOSFETs. More importantly, our experimental results demonstrated that stress-induced leakage current (SILC) caused by plasma damage can be significantly suppressed in N2O-nitrided oxides, compared to pure oxides, especially for pMOS devices. Finally, nitrided oxides were also found to be more robust when subjected to high temperature stressing. Therefore, nitrided oxides appear to be very promising for reducing plasma charging damage in future ULSI technologies employing ultrathin gate oxides View full abstract»

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  • Studies of high DC current induced degradation in III-V nitride based heterojunctions

    Page(s): 1421 - 1425
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    We report experiments on high dc current stressing in commercial III-V nitride based heterojunction light-emitting diodes. Stressing currents ranging from 100 mA to 200 mA were used. Degradations in the device properties were investigated through detailed studies of the current-voltage (I-V) characteristics, electroluminescence, deep-level transient Fourier spectroscopy and flicker noise. Our experimental data demonstrated significant distortions in the I-V characteristics subsequent to electrical stressing. The room temperature electroluminescence of the devices exhibited a 25% decrement in the peak emission intensity. Concentration of the deep-levels was examined by deep-level transient Fourier spectroscopy, which indicated an increase in the density of deep-traps from 2.7×1013 cm-3 to 4.2×1013 cm-3 at E1=E C-1.1 eV. The result is consistent with our study of 1/f noise, which exhibited up to three orders of magnitude increase in the voltage noise power spectra. These traps are typically located at energy levels beyond the range that can be characterized by conventional techniques including DLTS. The two experiments, therefore, provide a more complete picture of trap generation due to high dc current stressing View full abstract»

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  • Performance of the floating gate/body tied NMOSFET photodetector on SOI substrate

    Page(s): 1375 - 1384
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    In this paper, we report the performance of a new photodetector fabricated on SOI substrate using a standard CMOS process. The photodetector is formed by connecting the gate and the body of a NMOSFET. The gate-body terminal is left floating so that the potential can be modulated by illumination. The depletion region induced by the floating gate separates the optically generated electron-hole pairs in the direction perpendicular to the current. This increases the body potential and induces positive charges to the gate due to the tied gate and body. It results in a further turn on of the NMOSFET and extra optical current. The gain behavior under different illumination is characterized and explained by transistor theory. A wide signal range of more than six orders of magnitude and a high responsivity of about 1000 A/W have been obtained with an operating voltage as low as 0.2 V. The device scaling properties, noise behavior and transient response are also studied View full abstract»

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  • Light dependence of SOI MOSFET with nonuniform doping profile

    Page(s): 1469 - 1471
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    The light dependence of a fully depleted short channel silicon-on-insulator (SOI) MOSFET is investigated. As the photon flux density increases, there is a lowering in the surface potential barrier called the photon induced barrier lowering (PIBL). The threshold voltage shows a logarithmic reduction with the increase in the incident flux density. The drain source current and the transconductance significantly increase under the incident optical flux density. The device will be useful for high speed application in optical systems View full abstract»

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  • Effect of vacuum ultraviolet radiation on the gap fill properties of Teflon amorphous fluoropolymer film deposited by direct liquid injection

    Page(s): 1463 - 1465
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    In this work, the roles of vacuum ultraviolet (VUV) photons in improving the gap fill properties of a low dielectric constant (K) material (Teflon amorphous fluoropolymer, K=1.93) deposited by direct liquid injection assisted rapid photothermal chemical vapor deposition technique are discussed. A qualitative explanation is presented wherein it is proposed that high-energy photons provide photoexcitation of the species involved in the deposition of Teflon AFTM, thereby lowering the activation energy and migrational enthalpy required for surface diffusion leading to a higher molecular mobility on the patterned surface View full abstract»

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  • Comparison of hole and electron intersubband absorption strengths for quantum well infrared photodetectors

    Page(s): 1325 - 1329
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    It is well known that the hole intersubband absorption of normally incident (TE polarized) radiation is nonzero for p-doped quantum well infrared photodetectors (p-QWIP's) which have been fabricated without an optical grating. This present paper shows from k&oarr;·p&oarr; theory that, for typical p-QWIP designs, this hole intersubband absorption of TE polarized radiation (without the help of an optical grating) is significantly smaller than the electron intersubband absorption of TE polarized radiation in those n-doped QWIP's (n-QWIP's) fabricated with an optical grating. A second result of this present work is that, even when there is significant mixing of the light and heavy hole states, the p-QWIP absorption of TE polarized radiation (without the help of an optical grating) is still much smaller than the n-QWIP absorption of TE polarized radiation (with the help of an optical grating). The reason is that the mixing of light and heavy hole states never increases the amount of |S⟩-symmetry in the mixed hole wave function beyond the amount of |S⟩-symmetry which was present in the unmixed, purely light hole state. Finally, this present paper shows from k&oarr;·p&oarr; theory that strained layer growth on an (001) substrate does not significantly affect the strength of the hole intersubband absorption. The reason is that the Hamiltonian describing uniaxially strained quantum wells has precisely the same (tetragonal) symmetry as the Hamiltonian describing carrier confinement in unstrained quantum wells. All of these results are important in choosing a QWIP device design View full abstract»

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  • Compact modeling of high-frequency distortion in silicon integrated bipolar transistors

    Page(s): 1529 - 1535
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    The high-frequency distortion behavior of integrated silicon bipolar transistors is investigated experimentally and theoretically. Single-tone measurements using an automated setup are performed on transistors with various sizes and of different type, that were fabricated in a state-of-the-art production process offering high-speed and high-voltage transistor versions. The measured data, which were taken on devices laid out in usual high-frequency test pads, are compared to the advanced compact model HICUM showing excellent agreement over input power, bias, and frequency. In addition, a simplified model is used together with a Volterra-series approach to identify the nonlinear effects that are most important at high frequencies View full abstract»

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  • Equations of state for silicon inversion layers

    Page(s): 1449 - 1456
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    The accuracy of a generalized diffusion-drift description known as density-gradient theory for modeling the quantized inversion layer on (100) Si is studied in detail by comparing its results with corresponding Schrodinger-Poisson calculations. A key element of density-gradient theory is the equation of state used to model the response of the electron gas. A variety of such equations are considered including new approaches for modeling the lifting of the conduction band valley degeneracy and for representing exchange-correlation effects. On the whole, the theory does remarkably well over a wide range of biases, oxide thicknesses, and doping concentrations. For shallow wells and for simulating the density deep inside the semiconductor density-gradient theory actually outperforms the quantum mechanical approach unless the latter includes large numbers of subbands. When comparing with experiment, neither theory works that well in a predictive sense because of uncertainties in the treatment of the oxide and of the gate View full abstract»

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  • Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

    Page(s): 1393 - 1400
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    Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications View full abstract»

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  • Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: Process window versus complexity

    Page(s): 1484 - 1491
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    The continuous downscaling of CMOS devices aims at cost reduction and performance improvement. Process development constantly faces new constraints and integrates breakthroughs to overcome them. In deep submicron CMOS generations, scalability is in part limited by conflicting needs for shallow silicided junctions and low junction leakage. Both requirements can be met using elevated source/drain (ES/D) architecture. Although this solution has long been established, its avoidable extra complexity has delayed its introduction in industrial mainstream technologies. However, as device scaling continues, process windows are reducing critically. As a result, E S/D architecture is attracting a growing interest. This paper reports on a 0.18 μm CMOS technology featuring ES/D made with sacrificial selective epitaxy. This technology is examined from the standpoints of manufacturability and performance improvement. In contrast to most ES/D approaches, the selective epitaxy is done after junction formation, resulting in increased process window. Our ES/D process leads to dc and rf device performance enhancements. Nevertheless, the same functionality gains were achieved by a fine-tuning of the reference conventional low-cost process. Process window reduction will require ES/D for generations below 0.13 μm View full abstract»

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  • Fabrication and analysis of deep submicron strained-Si n-MOSFET's

    Page(s): 1406 - 1415
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    Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si0.8Ge0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects View full abstract»

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  • Theory and small signal analysis for a new bipolar injection transit time device (BIPOLITT)

    Page(s): 1310 - 1314
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    We have proposed and analyzed a new millimeter and submillimeter wave transit time device, the bipolar injection and transit time diode (BIPOLITT). The theory and small signal analysis for a two-terminal type rf operation is presented here. The device structure is similar to a heterojunction bipolar transistor (HBT) with an rf floating base. The relatively longer base is utilized to achieve an injection-phase delay close to 180°. The collector depletion region is used as drift region. As an example, a BIPOLITT diode for 300-400 GHz operation is designed, and its small signal specific negative resistance is calculated to be about -3×10-7 Ω·cm2 View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology