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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 6 • Date June 2000

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Displaying Results 1 - 17 of 17
  • Corrections to "low-voltage analog circuit design based on biased inverting opamp configuration"

    Publication Year: 2000 , Page(s): 580
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (24 KB)  

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  • Power-of-two adaptive filters using tabu search

    Publication Year: 2000 , Page(s): 566 - 569
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    Digital filters with power-of-two or a sum of power-of-two coefficients can be built using simple and fast shift registers instead of slower floating-point multipliers, such a strategy can reduce both the VLSI silicon area and the computational time. Due to the quantization and the nonuniform distribution of the coefficients through their domain, in the case of adaptive filters, classical steepest descent based approaches cannot be successfully applied. Methods for adaptation processes, as in the least mean squares (LMS) error and other related adaptation algorithms, can actually lose their convergence properties. In this work, we present a customized Tabu Search (TS) adaptive algorithm that works directly on the power-of-two filter coefficients domain, avoiding any rounding process. In particular, we propose TS for a time varying environment, suitable for real time adaptive signal processing. Several experimental results demonstrate the effectiveness of the proposed method View full abstract»

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  • High-order vector sigma-delta modulators

    Publication Year: 2000 , Page(s): 493 - 503
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    An attractive technique, useful for the implementation of multibit sigma-delta (ΣΔ) converters, is the spectral shaping of the unknown errors introduced by the analog circuitry of the digital-to-analog conversion (DAC). This is achieved by encoding the multibit ΣΔ sequence of the modulator output to an array of single-bit ΣΔ sequences. In this paper, it is shown how a multibit ΣΔ converter can be implemented directly using an array of M joint single-bit ΣΔ modulators, the vector ΣΔ modulator (VΣΔM). A model for stability and performance analysis of high-order VΣΔM is proposed. It is shown how the structure of the VΣΔM is modified in order to encode a PCM signal to an array of single-bit ΣΔ sequences. Simulations are carried out in order to show the successful operation of high-order VΣΔM's, and check the validity of the proposed model View full abstract»

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  • A comparison of noise-shaping clock generators for switched-capacitor filters

    Publication Year: 2000 , Page(s): 544 - 547
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    A programmable clock generator that uses noise shaping can generate a wide range of sampling frequencies with fine resolution for switched-capacitor filters (SCFs). In this brief, different noise-shaping transfer functions for such a clock generator are compared through simulation and measurement of two SCFs driven by the clock generator. A tone detector that uses a bandpass SCF driven by the programmable sampling-clock generator is also described View full abstract»

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  • Design of discrete coefficient FIR and IIR digital filters with prefilter-equalizer structure using linear programming

    Publication Year: 2000 , Page(s): 562 - 565
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    Optimal methods for designing multiplierless finite-impulse response (FIR) and infinite-impulse response (IIR) filters with cascaded prefilter-equalizer structures are proposed. Assuming that an FIR filter consists of a cyclotomic polynomial (CP) prefilter and an interpolated second order polynomial (ISOP) equalizer, in the proposed method, the prefilter and equalizer are simultaneously designed using mixed integer linear programming (MILP). The resulting filter is a cascaded filter with minimal complexity. For IIR filters, all-pole IIR equalizers consisting of inverse of interpolated first order polynomials (IIFOP's) are introduced, and a CP-prefilter cascaded with this type of equalizer is designed. Design examples demonstrate that the proposed methods produce a more efficient cascaded prefilter-equalizer than existing methods View full abstract»

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  • High-performance digit-serial complex multiplier

    Publication Year: 2000 , Page(s): 570 - 572
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    The authors present a fast highly regular digit-serial complex multiplier (CMUL) architecture which is well suited for VLSI implementations. They make two contributions. First, several complex-number representation schemes are discussed. It is shown that the proposed real-imaginary alternate scheme is the best among all representation schemes and the prior designs of CMUL's based on the radix-(2j) Redundant Complex Number System (RCNS) are not efficient with respect to hardware complexity and processing speed. Second, digit-serial CMUL architectures which can be pipelined at fine-grain level to increase the throughput rate are designed based on the carry-save configuration. The proposed design methodology can also result in low-power dissipation due to the reduced wiring complexity and glitching activity View full abstract»

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  • A 102-dB spurious-free DR ΣΔ ADC using a dynamic dither scheme

    Publication Year: 2000 , Page(s): 531 - 535
    Cited by:  Papers (4)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    A sigma-delta analog-to-digital converter (ADC) using dynamic dither to achieve a tone-free dynamic range of 102 dB in an audio bandwidth is presented. The design was implemented using a third-order 2:1 cascade architecture with an oversampling ratio of 128. The ADC modulator consumes 22 mW from a 3.0 V power supply, and was fabricated in 0.6-μm CMOS (analog portion) and 0.3-μm CMOS (digital portion) using multichip-module technology View full abstract»

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  • On the design of a fourth-order continuous-time LC delta-sigma modulator for UHF A/D conversion

    Publication Year: 2000 , Page(s): 518 - 530
    Cited by:  Papers (26)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    We consider the design and test of a fourth-order bandpass delta-sigma modulator (ΔΣM) for conversion of UHF analog signals to the digital domain for heterodyning and processing there. A prototype modulator in 0.5-μm SiGe presented in the second part of the paper achieved 40 dB of dynamic range in a 20-MHz bandwidth centered at 1 GHz and consumed 450 mW from a single 5-V supply. At the time this modulator was designed, no explicit design procedure to achieve a certain modulator performance level had been established. The first part of this paper, therefore, is devoted to explaining the tradeoffs involved in choosing the parameters for a gigahertz-clocking transconductor/LC-based ΔΣM and formulating such an explicit design procedure. Finally, we elucidate some further design considerations, redesign the prototype to improve its simulated performance, and discuss the general appropriateness of high-speed continuous-time ΔΣM for UHF analog-to-digital conversion View full abstract»

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  • Minimax design of FIR digital all-pass filters

    Publication Year: 2000 , Page(s): 576 - 580
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    This paper considers the design of digital all-pass finite impulse response filters in the minimax sense. Our proposed algorithm is a numerical technique to obtain the optimal filter coefficients by using a primal affine scaling variant of Karmarkar's algorithm. Under this approach, we formulate the design problem in terms of minimizing the magnitude and phase errors simultaneously or minimizing the magnitude and group delay errors simultaneously. Computer simulation shows the effectiveness of the proposed design techniques View full abstract»

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  • Degradation of the tracking performance of adaptive filtering algorithms with data correlation

    Publication Year: 2000 , Page(s): 559 - 561
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (84 KB)  

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  • Angle-constrained IIR filter pipelining for reduced coefficient sensitivities

    Publication Year: 2000 , Page(s): 555 - 559
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    Lookahead pipelining methods can be efficiently used for high sample rate or low-power applications of digital recursive filters. However, pipelined recursive filters cannot be implemented using the conventional cascade or parallel structures with second-order sections, since pipelining is achieved by introducing additional cancelling poles and zeros. Thus, if the poles of the pipelined filters are tightly crowded, it is possible that the pipelined filters suffer from large coefficient sensitivities. In this work, an angle-constrained filter design approach using a modified Remez exchange algorithm is proposed to avoid tight pole-crowding in pipelined filters by scattered lookahead. In addition to the reduced coefficient sensitivities, the constrained poles satisfy the pipelining property without pole-zero cancellation, which leads to hardware-efficient design View full abstract»

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  • A foveated silicon retina for two-dimensional tracking

    Publication Year: 2000 , Page(s): 504 - 517
    Cited by:  Papers (43)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    A silicon retina chip with a central foveal region for smooth-pursuit tracking and a peripheral region for saccadic target acquisition is presented. The foveal region contains a 9×9 dense array of large dynamic range photoreceptors and edge detectors. Two-dimensional direction of foveal motion is computed outside the imaging array. The peripheral region contains a sparse array of 19×17 similar, but larger, photoreceptors with in-pixel edge and temporal on-set detection. The coordinates of moving or flashing targets are computed with two one-dimensional centroid localization circuits located on the outskirts of the peripheral region. The chip is operational for ambient intensities ranging over six orders of magnitude, targets contrast as low as 10%, foveal speed ranging from 1.5 to 10 K pixels/s, and peripheral ON-set frequencies from <0.1 to 800 kHz. The chip is implemented in a 2 μm n-well CMOS process and consumes 15 mW (Vdd=4 V) in normal indoor light (25 μW/cm2). It has been used as a person tracker in a smart surveillance system and a road follower in an autonomous navigation system View full abstract»

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  • New sense amplifier for small-swing CMOS logic circuits

    Publication Year: 2000 , Page(s): 573 - 576
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (108 KB)  

    Novel differential edge-triggered sense amplifier (SA) capable of cascade connection is presented, the proposed SA can be used in memory units, as a line receiver and as a restoring element for small-swing logic. Cascade connection of the SA allows logic functions to be performed on small-swing differential signals directly, thus reducing delay and power View full abstract»

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  • Design of low-voltage bandgap reference using transimpedance amplifier

    Publication Year: 2000 , Page(s): 552 - 555
    Cited by:  Papers (44)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB)  

    The minimum supply voltage for implementing a typical bandgap reference is usually over 1.8 V. This minimum is mainly due to the limited input common-mode range of the opamp used in the bandgap reference. In this work, a low-voltage bandgap reference using a transimpedance amplifier that does not have this limitation is proposed and some of the design considerations for the proposed technique are briefly discussed. Based on this technique, a 1.2-V bandgap reference was implemented in a 1.2-μm CMOS process (VTN≈0.53 V and VTP≈-0.91 V) with bipolar option. The variations of the output voltage over temperature (0°C⩽T⩽100°C) were measured to be less than ±1% View full abstract»

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  • A current-mode exponential amplifier

    Publication Year: 2000 , Page(s): 548 - 552
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    The authors present an analog circuit architecture that implements the function f(x, y)=x·ea·y, where f(·,·),x and y are expressed by currents. An important property of this circuit is that x and y may either be positive or negative. The design of this circuit is based on the translinear principle, and suits IC implementation. The motivation for the development of this circuit is the need for f(x, y) as a building block in a neural network; however, the use of this circuit is not limited to neural networks View full abstract»

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  • Low-power scheduling with resources operating at multiple voltages

    Publication Year: 2000 , Page(s): 536 - 543
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB)  

    This paper presents a resource-constrained scheduling scheme and a latency-constrained scheduling scheme that minimize power consumption for the case when the resources operate at multiple voltages. The resource-constrained scheduling reduces the power consumption by maximally utilizing resources operating at reduced voltages and, at the same time, reducing the latency. The latency-constrained scheduling scheme reduces the power consumption by assigning as many nodes (of the data flow graph) as possible to the resources operating at reduced voltages. Both schemes consider the effect of switching activity on the power consumption of the functional units. In addition, both schemes use heuristics to reduce the power consumed by the level shifters. Experiments with HLS benchmark examples show that the proposed schemes achieve significant power reduction when the operating voltages are 5 and 3.3 V or 5, 3.3, and 2.4 V View full abstract»

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  • Degradation of the tracking performance of adaptive filtering algorithms with data correlation

    Publication Year: 2000 , Page(s): 559 - 561
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (28 KB)  

    Degradation of the tracking performance of adaptive filtering algorithms with data correlation is analyzed. The analysis is done in the context of the identification of a randomly time varying plant. Five algorithms are considered. They are least mean square, recursive least squares, sign, signed regressor, and sign-sign algorithms. The analysis is done in terms of the steady-state excess mean-square error and the steady-state mean-square weight misalignment. The degradation measure adopted is the ratio of the performance index for correlated data to that for white data View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope