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Advanced Packaging, IEEE Transactions on

Issue 2 • Date May 2000

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Displaying Results 1 - 25 of 29
  • Foreword additional contributions from the 49th electronic components and technology conference

    Publication Year: 2000 , Page(s): 164
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    Freely Available from IEEE
  • Foreword contributions from TC- 18 wafer scale packaging [Guest Editor]

    Publication Year: 2000 , Page(s): 197
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    Freely Available from IEEE
  • Agilent technologies' singlemode small form factor (SFF) module incorporates micromachined silicon, automated passive alignment, and non-hermetic packaging to enable the next generation of low-cost fiber optic transceivers

    Publication Year: 2000 , Page(s): 182 - 187
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    Agilent Technologies (formerly Hewlett-Packard) are currently manufacturing a range of multimode and singlemode (SM) SFF transceivers with data rates from 125 Mb/s to 1.25 Gb/s (higher data rates are being developed). This paper will address the singlemode module design, assembly techniques and performance. The SFF transceivers offer the same functionality as SC duplex transceivers but utilize the mini MT-RJ optical interface in order to achieve twice the port density. Test results that demonstrate the performance of the mini MT-RJ optical interface will be presented. The SFF modules are price competitive with SC duplex modules, and are designed to enable low cost, high volume manufacture. In order to meet the size constraints and achieve low manufacturing costs, the SM SFF transceiver utilizes silicon as a base to support the optical fibers and active components, and as an aid to passively align of the active components to the fibers. Most other passively aligned modules require the use of a more expensive expanded mode region laser diode (LD). But Agilent Technologies have developed a unique passive align and attach system that can easily achieve the required coupling power for fast ethernet, OC3 and gigabit ethernet using a standard 1300 mn Strained Multiquantum Well (SMQW) LD. The module design and the methods used for passive align will be discussed, as will the precision die attach (PDA) equipment. All precious Agilent Technologies/Hewlett-Packard SM modules relied on an Hermetic cavity around the active devices to achieve the reliability assurance, e.g., as defined in Bellcore TA-NWT-000983, but this type of Hermetic design has limited potential for cost reduction. The SM SFF module is designed to meet the same assurance levels, but uses silicone encapsulation in place of Hermeticity, and the results of the qualification testing will be presented View full abstract»

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  • Effect of randomness of Cu-Sn intermetallic compound layer thickness on reliability of surface mount solder joints

    Publication Year: 2000 , Page(s): 277 - 284
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    A statistical reliability analysis on thermal fatigue lifetime of surface mount solder joints, considering randomness of Cu-Sn intermetallic compound (IMC) layer thickness, is presented. Based on published thermal fatigue life test data, the two-parameter Weibull distribution of the thermal fatigue lifetime for a fixed IMC layer thickness is found, and a K-S goodness-of-fit test is conducted to examine the goodness of fit of the assumed Weibull distribution. Then, the Weibull parameters as functions of IMC layer thickness are obtained. Considering the randomness of IMC layer thickness, the MTTF and reliability of surface mount solder joints on thermal cycles are analyzed. For surface mount solder joints formed under the same conditions and loaded during the same thermal cycling as stated in the publication, numerical results of the MTTF and reliability are presented. The results show that when the mean value of MC layer thickness is low (e.g., smaller than 1.5 μm), the effect of randomness of IMC layer thickness is significant; i.e., the MTTF has strong dependence on IMC layer thickness distribution; and the reliability is significantly different at high thermal cycles. When the mean value of IMC layer thickness is high (e.g., greater than 2.0 μm), the effect of randomness of IMC layer thickness is negligible. Therefore, the presented results are important to the reliability study of surface mount solder joints. Even though the validity of the presented results based on the test data remains to be verified from other sources of data, the proposed statistical method is generally applicable for thermal fatigue reliability analysis of surface mount solder joints. By combining the proposed method with the forming mechanism of IMC layer under varying manufacturing and loading conditions, a comprehensive reliability analysis on thermal fatigue lifetime of surface mount solder joints can be expected View full abstract»

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  • Wafer-level chip scale packaging: benefits for integrated passive devices

    Publication Year: 2000 , Page(s): 247 - 251
    Cited by:  Papers (12)
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    Chip scale packaging continues to draw attention for applications that require high performance or small form factor solutions. The term chip scale package (CSP) has become synonymous with “fine pitch BGA” as the distinction between a ball grid array (EGA) and some chip scale packages becomes nearly indistinguishable. The cost of chip scale packages also continues to draw attention as one of the barriers to wide scale industry adoption. Sometimes lost in the chip scale debate is the discussion about wafer level chip scale packages, which offer the fastest path to small form factor, high performance and cost effective solutions. In this paper, we describe an approach to wafer level chip scale packaging that is an extension of integrated passive device processing, which results in low cost View full abstract»

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  • A minimal CSP

    Publication Year: 2000 , Page(s): 206 - 211
    Cited by:  Papers (4)
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    A chip scale package (CSP) using wafer scale processing was developed for a line of low cost, small form factor integrated circuits. The package uses polymeric repassivation and electrodeposited solder bumps connected by a unique conductor patterning method. The finished package resembles a common chip resistor. Reliability testing was used to optimize the bump design and the assembly methodologies. Field performance of more than 20 million packages has validated the test results View full abstract»

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  • Wafer-level chip size package (WL-CSP)

    Publication Year: 2000 , Page(s): 233 - 238
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    Size reduction is one of the main driving forces for packaging in nearly all electronic applications. The interaction of size reduction with highest functionality and high reliability is also predominant for all microelectronic systems. Therefore a synergism of optimal product design, smallest single chip package and board technology will give the best solution. Wafer level CSP will be the best solution for single chip packaging matching all requirements for electronic systems and reducing total cost View full abstract»

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  • MicroSMD-a wafer level chip scale package

    Publication Year: 2000 , Page(s): 227 - 232
    Cited by:  Papers (12)  |  Patents (1)
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    This paper outlines National Semiconductor's concept of wafer level chip scale package-also known as microSMD. This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability View full abstract»

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  • Development of three-dimensional memory die stack packages using polymer insulated sidewall technique

    Publication Year: 2000 , Page(s): 252 - 256
    Cited by:  Papers (4)  |  Patents (2)
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    A newly designed three dimensional (3-D) memory die stack package has been established, and the prototype of the 3-D package using mechanical dies has been successfully demonstrated. Fabrication processes of the 3-D package consist of: (1) wafer cutting into die segments; (2) die passivation including sidewall insulation; (3) via opening on the original I/O pads; (4) I/O redistribution from center pads to sidewall; (5) bare die stacking using polymer adhesive; (6) sidewall interconnection; and (7) solder balls attachment. There are several significant improvements in this new 3-D package design compared with the current 3-D package concept. The unique feature of this newly developed package is the sidewall insulation of dies prior to the I/O redistribution of dies, which produces (1) better chip-to-wafer yields and (2) significant process simplification during subsequent fabrication steps. According to this design, 100% of die yields on a conventional wafer design can be obtained without any neighboring die losses which usually occur during the I/O redistribution processes of conventional 3-D package design. Furthermore, the new 3-D package design can simplify the following processes such as I/O redistribution, sidewall insulation, sidewall interconnection, and package formation. It is proven that the mechanical integrity of the prototype 3-D stacked package meets requirements of the JEDEC Level III and 85°C/85% test View full abstract»

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  • Wafer level chip scale packaging (WL-CSP): an overview

    Publication Year: 2000 , Page(s): 198 - 205
    Cited by:  Papers (86)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    Several wafer level chip scale package (WLCSP) technologies have been developed which generate fully packaged and tested chips on the wafer prior to dicing. Many of these technologies are based on simple peripheral pad redistribution technology followed by attachment of 0.3-0.5 mm solder balls. The larger standoff generated by these solder balls result in better reliability for the WLCSP's when underfill is not used than for equivalent flip chip parts. RambusTM RDRAM and integrated passives are two applications that should see wide acceptance of WLCSP packages View full abstract»

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  • Sensitivity analysis of multiconductor transmission lines and optimization for high-speed interconnect circuit design

    Publication Year: 2000 , Page(s): 132 - 141
    Cited by:  Papers (12)
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    Sensitivity analysis of multiconductor transmission lines is derived from a new, all-purpose multi-conductor transmission line model in both frequency domain and time domain. Computer implementation of this new model as well as the sensitivity analysis has been completed. It enables efficient, accurate simulations of interconnect circuit responses as well as sensitivity analysis with respect to both electrical and physical transmission line parameters. By applying sensitivity analysis to high-speed interconnect circuit design, design variables are optimized to achieve simultaneous minimization of crosstalk, delays and reflections at desired nodes in the circuit without violating any indispensable design rules. Numerical examples are presented to demonstrate the validity of the proposed sensitivity analysis and illustrate its application to the optimization of high-speed interconnect circuit design View full abstract»

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  • A novel robust and low cost chips package and its thermal performance

    Publication Year: 2000 , Page(s): 257 - 265
    Cited by:  Papers (8)  |  Patents (2)
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    In an attempt to provide a high density memory solution, especially for workstation and PC servers, a stack chips package (SCP) has been developed. The major characteristics of SCP are as follows: (1) SCP contains a plurality of both memory chips and lead frames within a molded plastic package; (2) chip selection is made through the wire bonding option, resulting in the package with a memory capacity twice or four times that of monolithic chip; (3) plural lead frames are electrically interconnected all at once, using metal solders electroplated on the lead frame surface; and (4) SCP is found reliable and cost competitive when compared to other stack packages because it basically adopts the molded plastic packaging technology as well as the metal solder interconnection method. As electrical interconnection methods, both a fluxless soldering joint of Ag/Sn and a high-pressure mechanical joint of Ag were evaluated extensively and they successfully provided a reliable electrical conduction path without any signal degradation. Temperature cycle test and pressure cooker test were proved not to produce any micro cracks across the joint. The thermal performance of SCP was simulated by a thermal model based on finite element method (FEM) and also experimentally verified, showing good agreement within 10% deviation from simulated value. 128M SCP showed better thermal performance than stacked two TSOP's because one chip could serve as a heat sink while the other chip is activated and thermal conduction path through the lead frame is short View full abstract»

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  • 2 Gbit/s small form factor fiber-optic transceiver for single mode optical fiber

    Publication Year: 2000 , Page(s): 176 - 181
    Cited by:  Papers (13)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    Small form factor (SFF) optical transceivers are expected to be commonly used in the near future for high-end (high bit-rate, single mode) applications as well as for low-cost applications. SFF optical transceivers require new packaging techniques for the optical portion, because the distance between input and output optical axes is much smaller than those of conventional transceivers, e.g., the “1by9” type. Two types of optical packaging are introduced, both of which are suitable for transceivers which have an MT-based receptacle for single mode applications. One of the packaging types, a fiber-bulk structure, takes full advantage in cost and reliability of standard, hermetically sealed TO-canned optical devices. A conventional TO-can packaged laser diode (LD) and photodiode (PD) are held with short optical fibers by low-cost, injection-molded polymer retainers. The short fibers are connected to an MT ferrule inside the transceiver. An alternative packaging type, a surface mount structure, is intended for drastic cost reduction in large volume production by using advanced highly integrated assembly. An LD chip with an integrated spot-size converter and a waveguide-structured PD chip are mounted on a Si-substrate. Optical coupling between the optical devices and fibers on V-groove is accomplished by passive alignment, which reduces assembling time. A prototype transceiver with an MPO receptacle has been developed using the former packaging structure. Evaluated results show performance which complies with the 2.125 Gbit/s Fiber Channel standard. SFF transceivers with these new packaging technologies are expected to increase the optical port density and also to reduce the cost of high-end systems with bit rate of 2 Gbit/s or higher per port View full abstract»

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  • Ultrathin wafer level chip size package

    Publication Year: 2000 , Page(s): 212 - 214
    Cited by:  Papers (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products View full abstract»

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  • A comparison of hourly versus daily testing methods for evaluating the reliability of water soluble fluxes

    Publication Year: 2000 , Page(s): 285 - 292
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    This paper presents background on surface insulation resistance (SIR) testing and reports on its application to six water-soluble fluxes, and two hot-air solder leveling (HASL) fluids. This work evaluates two electrical reliability-testing methods. One method recorded SIR readings on a daily basis, the other on an hourly basis. During the twenty-eight day test, increased frequency of testing was more successful in detecting discrete electrical events, such as surface dendrites but not subsurface conductive anodic filaments (CAF). These failure mechanisms are sporadic in nature as they initiate, grow, short out and disintegrate, reform, then short out again. Unless a measurement is taken during the time when shorting is about to occur, they will not be detected electrically. Surface dendrites due to water condensation were easily detected with the hourly SIR method but not with the daily measurements. Unfortunately, neither the daily nor hourly SIR methods detected the presence of conductive anodic filaments (CAF). These results demonstrate the importance of visual examination of circuit assemblies after environmental testing, as well as highlighting the need for a more sensitive electrical reliability test method View full abstract»

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  • Application of the Taguchi method to chip scale package (CSP) design

    Publication Year: 2000 , Page(s): 266 - 276
    Cited by:  Papers (24)
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    A three-dimensional (3-D) nonlinear finite element model of an overmolded chip scale package (CSP) on flex-tape carrier has been developed by using ANSYSTM finite element simulation code. The model has been used to optimize the package for robust design and to determine design rules to keep package warpage within acceptable Joint Electron Device Engineering Council (JEDEC) limits. An L18 Taguchi matrix has been developed to investigate the effect of die thickness and die size, mold compound material and thickness, flex-tape thickness, die attach epoxy and copper trace thicknesses, and solder bail collapsed stand-off height on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling 125°C to -40°C. This condition is approximated by cooling the package which is mounted on a multilayer printed circuit board (PCB) from 125°C to -40°C. For solder ball coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 25°C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, the package should have smaller die with thicker overmold. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of solder ball with the highest strain level. The results indicate that the highest strain levels are attained in solder balls located at the edge of the die. The strain levels could then be used to predict the fatigue life of individual solder balls View full abstract»

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  • Ultra CSPTM-a wafer level package

    Publication Year: 2000 , Page(s): 220 - 226
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSPTM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed View full abstract»

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  • New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design

    Publication Year: 2000 , Page(s): 303 - 312
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    A new simple but accurate simultaneous-switching-noise (SSN) model for complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) package design was developed. Since the model is based on the sub-micron metal-oxide-semiconductor (MOS) device model, it can predict the SSN for today's sub-micron-based very large scale integration (VLSI) circuits. In order to derive the SSN model, the ground path current is determined by taking into account all the circuit components such as the transistor resistance, lead inductance, load capacitance, and oscillation frequency of the noise signal. Since the current slew rate is not constant during the device switching, a rigorous analysis to determine the current slew rate was performed. Then a new simple but accurate closed-form SSN model was developed by accurately determining current slew rate for SSN with the alpha-power-law of a sub-micron transistor drain current. The derived SSN model implicitly includes all the critical circuit performance and package parameters. The model is verified with the general-purpose circuit simulator, HSPICE. The model shows an excellent agreement with simulation even in the worst case (i.e., within a 10% margin of error but normally within a 5% margin of error). A package design methodology is presented by using the developed model View full abstract»

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  • Passively aligned LD/PD array submodules by using micro-capillaries

    Publication Year: 2000 , Page(s): 323 - 327
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    A passive alignment technique using micro-capillaries has been developed for multichannel optical interconnection modules. The technique is applicable when coupling a four-channel LD array to a hemispherically lensed fiber array, or a four-channel PD array to a slant-polished fiber array. Alignment time was reduced to less than 1/20 that of conventional active alignment by simply positioning the fiber array through capillaries in V grooves in the Si-platform, while obtaining high coupling efficiency of -3.4±0.5 dB for LD submodules and -0.4±0.1 dB for PD submodules View full abstract»

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  • Improved thermal fatigue reliability for flip chip assemblies using redistribution techniques

    Publication Year: 2000 , Page(s): 239 - 246
    Cited by:  Papers (12)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    The bond pad design on a chip can be reconfigured to a new pad design using a redistribution layer, based on multichip module-deposited (MCM-D) technology. The new pad configuration can be used for flip chip mounting. The thermo-mechanical reliability of these redistributed flip chip structures is in particular determined by the visco-plastic deformations of the solder joints and by the stresses in the photosensitive BCB redistribution layers. In this paper, the influence of this redistribution layer on the solder joint reliability is investigated. Also the induced stresses in this redistribution layer may not exceed the ultimate stress level. Three different redistribution processes are considered. Finite element simulations and Coffin-Manson based reliability models are used to compare the thermal cycling reliability of redistributed and standard flip chip assemblies. The existence of a photosensitive BCB redistribution layer on the chip influences the thermal fatigue of solder joints. The largest reliability improvement using redistributed chips is achieved by moving the solder joints from the perimeter to the interior of the die resulting in an area array flip chip View full abstract»

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  • Pole-residue formulation for transient simulation of high-frequency interconnects using householder LS curve-fitting techniques

    Publication Year: 2000 , Page(s): 142 - 147
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    As digital circuits approach the GHz range, and as the need for high performance wireless devices increases, new simulation tools which accurately characterize high frequency interconnects are needed. In this paper, a new macromodeling algorithm for time domain simulation of interconnects is presented. The algorithm incorporates Householder LS curve-fitting techniques. The approach generates a universal macromodeling tool that enables simulation of interconnects in a modified version of simulation program with integrated circuit emphasis (SPICE). This results in a method that conveniently incorporates accurate EM models of interconnects or experimental data into a circuit simulator. The time domain simulation results using this new tool are compared with results from other simulators View full abstract»

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  • SuperCSPTM

    Publication Year: 2000 , Page(s): 215 - 219
    Cited by:  Papers (41)  |  Patents (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (108 KB)  

    SuperCSP is fabricated by building up the interposer with high reliability encapsulant on the chip by wafer level packaging technology. New encapsulation technology enables real chip-sized package from a package perspective. It is also a known good encapsulated die (KGED) from a die perspective. The reasons why board level reliability of SuperCSP is good regardless of extremely low bump-standoff height are as follows. (1) The C.T.E of encapsulant for SuperCSP is close to that of motherboard, so that the encapsulant layer effectively reduces stress occurring in the solder interconnecting portion. (2) Encapsulant with high adhesive strength reinforces and fixes the delicate connecting portion of chip and post, and also does not allow its deformation. (3) Connecting portion of solder ball and post has a strong structure and can tolerate the stress because solder balls catch hold of the whole surface of metal posts, which stick out from the encapsulant and have a mound like structure View full abstract»

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  • Performance comparison of small form factor fiber optic connectors

    Publication Year: 2000 , Page(s): 188 - 196
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    A comparison of small form factor (SFF) fiber optic connectors is presented for LC, MT-RJ, SC-DC, and VF-45. Multimode jumper cables were tested using industry standard test procedures and bench marked against the industry standard SC Duplex connector. Initial loss data as well as stress testing was performed. Variations were found in the performance of the connectors types and between connectors of the same type from different suppliers. In some cases the connectors out performed the SC Duplex on some tests but no connectors out performed the SC Duplex on all tests with the mechanical stress tests of axial and off-axial pull being the most difficult to exceed. These connectors are rapidly developing and are at different levels of maturity but none of them tested out to be a fully mature replacement for the SC Duplex connector yet View full abstract»

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  • Spectroscopic measurement of mounting-induced strain in optoelectronic devices

    Publication Year: 2000 , Page(s): 170 - 175
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB)  

    Mounting-induced strain in high-power laser diodes is studied by noninvasive photocurrent (PC) spectroscopy. We demonstrate that the strain can be determined with high accuracy by means of Fourier-transform (FT) photocurrent measurements. The optical transitions within the quantum well (QW) region of identical InAlGaAs/GaAs laser diodes which were mounted with different external strain have shown spectral shifts of up to 10 meV. The accuracy of the energy level shifts obtained by FT PC measurements is of 150 μ eV for the QW-region and 500 μeV for the waveguide region. The measured strain status of the active region is compared with model calculations to quantify the amount of strain which is transferred from the heat sink to the semiconductor device View full abstract»

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  • Factors influencing the permittivity of polymer/ceramic composites for embedded capacitors

    Publication Year: 2000 , Page(s): 313 - 322
    Cited by:  Papers (46)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    The effect of the polymer permittivity on the permittivity of the polymer/lead magnesium niobate-lead titanate (PMN-PT) composite was investigated using epoxies, polyimides, polycarboxylic acids, and poly(methyl methacrylate) (PMMA). The permittivity of the polymers (without ceramic loading) ranged from 2.8-4.6. The permittivity of the composites, except for epoxies, was found to agree with the value predicted by the Smith equation. Polyacrylic acid (PAA) was found to bond to the PMN-PT surface due to an acid-base reaction. Novolac epoxy was not found to interact strongly with PMN-PT. The results suggest that polycarboxylic acids can act as a surfactant to deagglomerate PMN-PT powder while epoxies might not. Hence, the lower permittivity found in the epoxy based composites may be due to particle agglomeration. Three out of eight phosphated ester type surfactants were shown to increase the composite permittivity, indicating that the most effective surfactants decreased agglomeration of the ceramic powder and improved the dispersion in the polymer matrix. The particle size of the PMN-PT in the same solvent as used in the composite experiment was reduced by the use of ball-milling with the aid of the surfactant. Assuming that agglomerated particles act as a larger particle, an electrostatic field simulation was used to determine that the reduction in particle size due to deagglomeration increased the permittivity of the composite. These results were confirmed by experiment View full abstract»

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Aims & Scope

IEEE Transactions on Advanced Packaging has its focus on the design, modeling, and application of interconnection systems and packaging: device packages, wafer-scale and multichip modules, TAB/BGA/SMT, electrical and thermal analysis, opto-electronic packaging, and package reliability.

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Ganesh Subbarayan
Purdue University, School of Mechanical Engineering