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Solid-State Circuits, IEEE Journal of

Issue 6 • Date June 2000

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Displaying Results 1 - 17 of 17
  • A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSM applications

    Page(s): 798 - 806
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    A receive baseband analog-to-digital converter (ADC) for a GSM cellular radio system is presented. Low voltage and low power techniques have been applied across many aspects of the design. The circuit consists of two second-order double-sampled semi-bilinear /spl Sigma//spl Delta/ modulators followed by two 576-tap digital finite-impulse response (FIR) GSM-channel filters with offset calibration. The complete ADC achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7-V supply. The area is 1.6 mm/sup 2/ in a 0.5-/spl mu/m n-well double-poly triple-metal CMOS process. View full abstract»

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  • A low-noise phase-locked loop design by loop bandwidth optimization

    Page(s): 807 - 815
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively. View full abstract»

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  • A CMOS two-path tree search detector

    Page(s): 816 - 825
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (322 KB)  

    Two-path tree search (TPTS) is a detection algorithm combining a decision-feedback equalizer and a two-path tree search estimator. This sub-optimal tree search overcomes the exponential increase in hardware complexity with tree length in a fixed-delay tree search structure. An adaptive mixed-signal CMOS TPTS detector is presented in this paper. The integrated circuit occupies 2.77 mm by 2.44 mm (including the bonding pads) in a 0.6 /spl mu/m CMOS process. It performs about 0.8 dB better than a conventional decision-feedback equalization for a disk drive read channel. View full abstract»

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  • A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

    Page(s): 826 - 834
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-/spl mu/m CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems. View full abstract»

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  • An architecture of high-performance frequency and phase synthesis

    Page(s): 835 - 846
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (543 KB)  

    Frequency synthesis has many applications in today's commercial electronic and telecommunication system design. Some techniques exist which can be used to generate a frequency that is an integer or fractional multiple of a reference frequency. This architecture is used to generate a signal of any desired frequency in a certain range from multiple reference signals with same frequency but different phases. These reference signals may come from a voltage-controlled oscillator (VCO) which is close looped with a reference clock by a phase-lock loop (PLL). This architecture provides some unique features, superior quality, and ease of implementation. In some cases, the synthesized frequency is time-average frequency. The signal can be treated as a carrier signal frequency modulated by another signal. Various phase-shifted versions and duty cycle versions of this signal can also be generated from this architecture. This architecture also has direct application to spread spectrum clock generation. View full abstract»

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  • Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications

    Page(s): 847 - 855
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (587 KB)  

    This paper describes the architecture and components of a high-speed clock and data recovery (CDR) circuit. Fully differential CMOS circuits are presented for an integrated physical layer controller of a 622-Mb/s (OC-12) system, although the design can be used in other systems with clock speeds in the 622-933-MHz range. Simulations and experimental results are presented for the building blocks including novel designs for a current-controlled oscillator (CCO) and a differential charge pump. The CCO is based on a two-stage ring oscillator. It consists of parallel differential amplifier pairs which reliably generate the necessary phase shift and gain to fulfill the oscillation conditions over process and temperature variations. Two test chips are implemented in 0.35-/spl mu/m CMOS. One contains partitioned building blocks of a phase-locked loop (PLL) which, together with an external loop filter, can be used for flexible testing and CDR applications. The other chip is a monolithic CDR with integrated loop filter. It exhibits a power consumption of 0.2 W and a measured rms clock jitter of 12.5 ps at 933 MHz. View full abstract»

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  • An all-digital low-power IF GPS synchronizer

    Page(s): 856 - 864
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (681 KB)  

    An all-digital intermediate frequency (IF) Global Positioning System (GPS) synchronizer for employment in portable electronic applications is presented. The chip performs code and carrier synchronization, decodes received data, and provides pseudorange estimates. To reduce the average power dissipation, the whole receiver is powered down and reactivated only when it needs to update its position estimate. With a lower duty cycle, the receiver spends more time in the power-down mode and the power consumption of the whole receiver is proportionately reduced. The synchronizer is therefore designed to minimize re-acquisition time between position readings. When powered up, the synchronizer searches in parallel over a window of timing uncertainty, then employs near-optimal tracking with a variable loop gain filter. With SNR=-20 dB, phase shift rate of 1 chip/s, and user velocity of 30 m/s, the synchronizer chip dissipates under 4 mW for pseudorange estimate rms error of under 7 m. View full abstract»

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  • nMOS reversible energy recovery logic for ultra-low-energy applications

    Page(s): 865 - 875
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (397 KB)  

    We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-/spl mu/m CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V/sub dd/=3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at V/sub dd/=0.9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption. View full abstract»

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  • Improved sense-amplifier-based flip-flop: design and measurements

    Page(s): 876 - 884
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (267 KB)  

    Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper. View full abstract»

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  • A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip

    Page(s): 885 - 894
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (741 KB)  

    A byte-slice datapath for exploring multi-chip RISC processor development in AlGaAs-GaAs heterojunction bipolar transistor (HBT) technology has been designed, fabricated and tested. The circuits are implemented using differential current-mode logic (CML) and emitter-coupled logic (ECL) with signal swings of 250 mV. Each datapath chip contains a single slice, including an 8-bit by 32-word single-port register file with a 230-ps read access time, and an 8-bit carry-select adder with a 140-ps select path and a 380-ps ripple-carry path. Each unpackaged die was tested using an at-speed boundary scan test scheme. The register file and adder carry chain are also implemented in a special test chip for accurate performance characterization of these critical circuits. View full abstract»

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  • A scalable substrate noise coupling model for design of mixed-signal IC's

    Page(s): 895 - 904
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (585 KB)  

    This paper describes a design-oriented scalable macromodel for substrate noise coupling in heavily-doped substrates. The model requires only four parameters which can be readily extracted from a small number of device simulations or measurements. Once these parameters have been determined, the model can be used in design for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated with measurements from test structures fabricated in a 0.5 /spl mu/m CMOS process. Applications of the model to circuit design are demonstrated with simulation results. View full abstract»

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  • On the use of MOS varactors in RF VCOs

    Page(s): 905 - 910
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB)  

    This paper presents two 1.8 GHz CMOS voltage-controlled oscillators (VCOs), tuned by an inversion-mode MOS varactor and an accumulation-mode MOS varactor, respectively. Both VCOs show a lower power consumption and a lower phase noise than a reference VCO tuned by a more commonly used diode varactor. The best overall performance is displayed by the accumulation-mode MOS varactor VCO. The VCOs were implemented in a standard 0.6 /spl mu/m CMOS process. View full abstract»

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  • A design for high noise rejection in a pseudodifferential preamplifier for hard disk drives

    Page(s): 911 - 914
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (179 KB)  

    A study of supply and system noise rejection for a pseudodifferential amplifier is presented in this paper. This pseudodifferential amplifier is aimed at high data-rate disk drive signal sensing and preamplification applications. This high rejection was achieved by improving the rejection of the pseudodifferential amplifier and also by carefully designing the interconnect flex circuit where the preamplifier is mounted. The measured rejection to power supply, ground and system noise is above 50 dB over a 300 MHz bandwidth. This is significant for a pseudodifferential amplification system. The gain of the preamplifier is 47 dB and write mode to read mode switching time is 210 ns. This preamplifier currently supports disk drive data rates over 270 Mb/s. View full abstract»

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  • A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission

    Page(s): 915 - 918
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    A large-swing, voltage-mode driver and an on-chip termination circuit are presented for high-speed nonreturn-to-zero (NRZ) data transmission through a copper cable. The proposed driver with active pull-up and pull-down can generate a 700-mV signal to deliver a 2 Gbaud serial NRZ data stream. Low output impedance offered by simple negative-feedback resistors alleviates the detrimental effect of the parasitic capacitance by supplying fast current impulses. A proposed on-chip termination circuit provides termination impedance to a mid-supply termination voltage with the benefit of reduced parasitic capacitance and better termination characteristics compared with off-chip termination. The driver and termination circuits have been incorporated in a 2 Gbaud transceiver chip and fabricated in 0.35 /spl mu/m CMOS technology. Measurements show a 1.4 V differential swing with a slew rate of 2.5 V/ns at the receiver output and a 65% reduction of reflection by the on-chip termination circuit with power consumption of 191 mW at 3.3 V supply. View full abstract»

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  • Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler"

    Page(s): 919 - 920
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (105 KB)  

    For the original paper see ibid., vol. 33, no. 10, p. 1568-1571 (1998). In the aforementioned paper a fast true single-phase clocking (TSPC) ratioed D-flip-flop is proposed by C. Yang et al. It is claimed by the commenters that the proposed flip-flop violates the edge-triggering characteristic. However, it is shown that high clock frequency and the propagation delay of the transistor enable the flip-flop to operate normally in the dual-modulus prescaler. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan