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Solid-State Circuits, IEEE Journal of

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Solid-State Circuits, IEEE Journal of

Issue 6 • Date June 2000

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A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSM applications

A low-noise phase-locked loop design by loop bandwidth optimization

A CMOS two-path tree search detector

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

An architecture of high-performance frequency and phase synthesis

Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications

An all-digital low-power IF GPS synchronizer

nMOS reversible energy recovery logic for ultra-low-energy applications

Improved sense-amplifier-based flip-flop: design and measurements

A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip

A scalable substrate noise coupling model for design of mixed-signal IC's

On the use of MOS varactors in RF VCOs

A design for high noise rejection in a pseudodifferential preamplifier for hard disk drives

A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission

Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler"

Correction to "CMOS high-frequency switched-capacitor filters for telecommunication applications"

Correction to "A fully integrated 0.5 - 5.5-GHz CMOS distributed amplifier"

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