IEEE Transactions on Computers

Issue 4 • Apr 2000

Filter Results

Displaying Results 1 - 7 of 7
  • Understanding why correlation profiling improves the predictability of data cache misses in nonnumeric applications

    Publication Year: 2000, Page(s):369 - 384
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (4112 KB)

    Latency-tolerance techniques offer the potential for bridging the ever-increasing speed gap between the memory subsystem and today's high-performance processors. However, to fully exploit the benefit of these techniques, one must be careful to apply them only to the dynamic references that are likely to suffer cache misses-otherwise the runtime overheads can potentially offset any gains. In this p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Generic universal switch blocks

    Publication Year: 2000, Page(s):348 - 359
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (572 KB)

    A switch block M with W terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most W) is simultaneously routable through M. In this paper, we present an algorithm to construct N-sided universal switch blocks with W terminals on each side. Each of our universal switch blocks has (2N View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Scheduling distributed real-time tasks with minimum jitter

    Publication Year: 2000, Page(s):303 - 316
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (972 KB)

    The problem of scheduling real-time tasks with minimum jitter is particularly important in many control applications; nevertheless, it has rarely been studied in the scientific literature. This paper presents an unconventional scheduling approach for distributed static systems where tasks are periodic and have arbitrary deadlines, precedence, and exclusion constraints. The solution presented in th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Least upper bounds for the size of OBDDs using symmetry properties

    Publication Year: 2000, Page(s):360 - 368
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB)

    This paper investigates reduced ordered binary decision diagrams (OBDD) of partially symmetric Boolean functions when using variable orders where symmetric variables are adjacent. We prove upper bounds for the size of such symmetry ordered OBDDs (SymOBDD). They generalize the upper bounds for the size of OBDDs of totally symmetric Boolean functions and nonsymmetric Boolean functions proven by M.A.... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A matroid-theoretic solution to an assignment problem in the conformance testing of communication protocols

    Publication Year: 2000, Page(s):317 - 330
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (500 KB)

    The minimum length test sequence generation method proposed previously (1988) for conformance testing of a protocol uses Unique Input Sequences (UIS) for state identification. This method, called the U-method, requires that the test graph, a graph derived from the protocol, be connected. This requirement also needs to be satisfied in the case of the MU-method, which assumes that the multiple UISs ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Extending value reuse to basic blocks with compiler support

    Publication Year: 2000, Page(s):331 - 347
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (7232 KB)

    Speculative execution and instruction reuse are two important strategies that have been investigated for improving processor performance. Value prediction at the instruction level has been introduced to allow even more aggressive speculation and reuse than previous techniques. This study suggests that using compiler support to extend value reuse to a coarser granularity than a single instruction, ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A hierarchical test generation approach for large controllers

    Publication Year: 2000, Page(s):289 - 302
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (456 KB)

    A testing approach targeted at Hardware Description Language (HDL)-based specifications of complex control devices is proposed. For such architectures, gate-level test pattern generators require insertion of scan paths to enable the flat gate-level representations to be efficiently handled. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Our appr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org