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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 8 • Date Aug 1988

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Displaying Results 1 - 11 of 11
  • Behavioral to structural translation in a bit-serial silicon compiler

    Publication Year: 1988, Page(s):877 - 886
    Cited by:  Papers (44)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB)

    After a brief discussion of previous work in the field of behavioral-to-structural translation, the bit-serial architecture which is the target of the bit-serial compiler is discussed. The bit-serial language (BSL) is then defined, and the details of the behavioral-to-structural translation are given View full abstract»

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  • Comparison of methods to calculate capacitances and cutoff frequencies from DC and AC simulations on bipolar devices

    Publication Year: 1988, Page(s):855 - 861
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    The question of whether or not the convenient stored-charge (SC) method is appropriate to calculate small-signal characteristics of bipolar devices is considered. A general definition of the total SC capacitance of a semiconductor device, and an expression for the difference with the AC capacitance are presented. The SC method is found to yield correct capacitance for practical p-n junction diodes... View full abstract»

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  • A logic-to-logic comparator for VLSI layout verification

    Publication Year: 1988, Page(s):897 - 907
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    The logic-to-logic comparator (LLC) is described as a tool that verifies VLSI layouts by comparing the logic diagrams for a circuit with structures extracted from the circuit's layout. LLC can operate at either the gate or the transistor level, although the gate level is preferred. It is similar to other graph-isomorphism-based tools, but incorporates some important improvements. The most importan... View full abstract»

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  • LES: a layout expert system

    Publication Year: 1988, Page(s):868 - 876
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    The LES expert system for layout generation of random logic modules in a hierarchical CMOS VLSI design system is described. It applies a combination of rule- and algorithmic-based techniques on a novel layout style. The layout style utilizes silicon area more efficiently than a previously developed style. Experimental results have demonstrated the superiority of this expert system against various ... View full abstract»

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  • On using signature registers as pseudorandom pattern generators in built-in self-testing

    Publication Year: 1988, Page(s):919 - 928
    Cited by:  Papers (50)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    Signature registers are commonly used to collect test responses in built-in self-testing (BIST). If the contents of signature registers can be used as test patterns, the overall testing time can be reduced due to improved testing parallelism. Moreover, the number of extra registers for implementing BIST could be reduced. Here, the characteristics of the patterns generated by signature registers ar... View full abstract»

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  • Extraction of BJT model parameters using optimization method

    Publication Year: 1988, Page(s):850 - 854
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A method for parameter extraction of a SPICE 2G.6 bipolar junction transistor (BJT) model is presented. The proposed approach consists of minimizing a nonlinear objective function to produce a least-squares fit of the model equations to a set of measured device characteristics. All parameters are extracted using a combination of the direct-search optimization method and the variable metric algorit... View full abstract»

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  • A technique for pull-up transistor folding

    Publication Year: 1988, Page(s):887 - 896
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    The authors consider the constraint limiting multiple folding in programmable logic array (PLA) layouts imposed by the layout architecture which positions pull-up transistors on the boundary of the cell and uses another metal layer to connect pull-ups to terms inside the PLA. The general PLA architecture supports only input- and output-port folding by sharing them in either the same column or the ... View full abstract»

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  • Mixed-mode PISCES-SPICE coupled circuit and device solver

    Publication Year: 1988, Page(s):862 - 867
    Cited by:  Papers (54)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    A computer program has been written to allow simultaneous solution of an electrical network containing both nonlinear circuit elements and two-dimensional finite-element solid-state models. The circuit solver is based on the popular SPICE-II program, while the PISCES-II program is used to model the solid-state devices. Both steady-state DC and time-dependent solutions are possible. Additional feat... View full abstract»

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  • Escher-a geometrical layout system for recursively defined circuits

    Publication Year: 1988, Page(s):908 - 918
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    An Escher circuit description is a hierarchical structure composed of cells, wires, connectors between wires, and pins that connect wires to cells. Cells may correspond to primitive circuit elements, or they may be defined in terms of lower level subcells. Unlike other geometrical layout systems, a subcell may be an instance of the cell being defined. When such a recursive cell definition is initi... View full abstract»

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  • The solution of a numerical problem encountered when adding a mobility model to a finite-element device simulator

    Publication Year: 1988, Page(s):929 - 930
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    The addition of a mobility model to a finite-element simulator was found to create a convergence problem identified with the addition of positive terms to the off-diagonal elements in the solution matrix. Fast convergence rates were recovered by carefully adjusting the solution matrix such that the off-diagonal elements in question were all nonpositive View full abstract»

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  • SLS-a fast switch-level simulator [for MOS]

    Publication Year: 1988, Page(s):838 - 849
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1124 KB)

    SLS, a large-capacity, high-performance switch-level simulator developed to run on an IBM System/370 architecture is described. SLS uses a model which closely reflects the behavior of MOS circuits. The high performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady-sta... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu