# IEE Proceedings - Circuits, Devices and Systems

## Filter Results

Displaying Results 1 - 9 of 9
• ### DC model of GaAs MESFETs improving circuit simulation

Publication Year: 2000, Page(s):139 - 145
Cited by:  Papers (1)
| | PDF (556 KB)

An improved DC model of low- and high-power GaAs MESFETs is proposed. The third-order dependence of fitting parameters on bias conditions is included. The main objective is to obtain a very good agreement between measured and simulated I-V curves, particularly in the knee and saturation regions, regardless of the technological characteristics of the device. The model has been compared with the mos... View full abstract»

• ### Effect of ionising radiation on the characteristics of a MOSFET

Publication Year: 2000, Page(s):133 - 138
| | PDF (616 KB)

The effect of radiation-induced changes on the characteristics of an n-channel MOSFET has been investigated theoretically. A one-dimensional semi-numerical model of the device has been developed which can estimate fairly accurate characteristics of the device under unirradiated and irradiated conditions. The effect of ionising radiation on the channel voltage and electric field profile in the chan... View full abstract»

• ### Analytical base transit time of integrated bipolar transistors in quasi-saturation and hard saturation

Publication Year: 2000, Page(s):129 - 132
| | PDF (336 KB)

Based on the assumption of negligible recombination within the thin epitaxial collector layer of an integrated bipolar transistor switch in quasi-saturation, solutions to the collector minority carrier profile and transit time in the induced base are derived. In contrast to Dai and Yuan's analysis (1997), the present analysis takes both the drift and diffusion currents into account and is valid fo... View full abstract»

• ### Analytical model for current transport in organic thin-film transistors

Publication Year: 2000, Page(s):125 - 128
| | PDF (348 KB)

The I-V characteristics of organic thin-film transistors are examined and a model is proposed that could explain the behaviour of the drain current in the subthreshold' mode. The model proposes that an injection current at the source dominates the subthreshold' current at positive gate voltage and the magnitude of this current is modulated by space charge residing in the bulk of the thin film. I... View full abstract»

• ### Design issues on high-speed high-resolution track-and-holds in BiCMOS technology

Publication Year: 2000, Page(s):100 - 106
Cited by:  Papers (17)  |  Patents (2)
| | PDF (692 KB)

The authors address some fundamental issues in track-and-hold (T and H) design. A number of explicit expressions characterising the main limitations of this class of circuits are given. A fully differential open-loop T and H is presented satisfying the stringent specifications imposed by present telecom applications. It exhibits high-resolution (12 bit) and high-speed (fck=160 MHz) as m... View full abstract»

• ### Large-signal transient analysis of a soft-switching, two-switch AC-to-DC converter

Publication Year: 2000, Page(s):146 - 152
Cited by:  Papers (1)
| | PDF (568 KB)

The paper presents large signal transient analysis of a two-switch, soft-switching, single-stage AC-to-DC converter using it discrete time domain analysis approach. Analysis is used to predict the behaviour of the converter for step changes in load and supply voltages. Theoretical results are verified by PSPICE simulation and experimental results View full abstract»

• ### Logical modelling of delay degradation effect in static CMOS gates

Publication Year: 2000, Page(s):107 - 117
Cited by:  Papers (15)
| | PDF (924 KB)

A delay model for static CMOS gates with application in gate level logic simulation is presented. It incorporates the degradation effect on narrow pulses and is named PID (pure, inertial and degradation). The results lead to the conclusion that the proposed new delay model maintains the high speed of gate-level logic simulation with a precision comparable to that of electrical simulation View full abstract»

• ### Fault coverage and defect level estimation models for partially testable MCMs

Publication Year: 2000, Page(s):119 - 124
| | PDF (576 KB)

The authors propose a simple and efficient mathematical model for designers to estimate fault coverage for partially testable multichip modules (MCMs). This model shows a relation between fault coverage, test methodology, and the fraction and distribution of design for testability (DFT) dies in MCMs. Experimental results show that the proposed model can efficiently predict the fault coverage of a ... View full abstract»

• ### Op-amp based CMOS field-programmable analogue array

Publication Year: 2000, Page(s):93 - 99
Cited by:  Papers (17)
| | PDF (700 KB)

The field-programmable analogue array (FPAA) is crucial to improving turnaround time for analogue circuit designs. The critical parameters when specifying the design are bandwidth and accuracy. FPAAs reported to date compromise one parameter when optimising the other. A new continuous-time FPAA architecture is presented which simultaneously achieves bandwidth and repeatability comparable to the ac... View full abstract»

## Aims & Scope

Published from 1994-2006, IEE Proceedings - Circuits, Devices and Systems contained significant and original contributions on electronic circuits, solid-state electronic devices and systems. It covered the following topics: circuit theory and design, circuit analysis and simulation; CAD; filters; circuit implementations; cells and architectures for integration including VLSI; testability, fault-tolerant design, minimisation of circuits; electronic devices for technologies including nanoelectronics and MEMs; device and process characterisation; device parameter extraction schemes; the mathematics of circuits and systems theory; and testing and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers.

Full Aims & Scope