By Topic

Computers and Digital Techniques, IEE Proceedings -

Issue 1 • Date Jan 2000

Filter Results

Displaying Results 1 - 8 of 8
  • Reducing test application time by scan flip-flops sharing

    Publication Year: 2000 , Page(s): 42 - 48
    Cited by:  Papers (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    The test application time is reduced while preserving the test quality or the fault coverage for circuit testing. The goal is achieved by reducing the number of scan flip-flops required for a scan-based design, and the basic procedure is to look for groups of “s-independent inputs.” The s-independent inputs in a group have the property that, when these inputs are combined together to share a scan flip-flop, the originally detectable faults are still detectable under the new scan structure. Though the number of test vectors may slightly increase, this can be offset by the significant reduction in the scan test width. Thus, the goal of test time reduction for scan test can be accomplished. For circuits which have few s-independent inputs, bypass storage cells are added to increase the s-independencies among all inputs. Experiments have been performed on MCNC benchmarks and the results are good. Several benchmark circuits have shown more than 90% of test time reduction View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • In-line test of synthesised systems exploiting latency analysis

    Publication Year: 2000 , Page(s): 33 - 41
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (828 KB)  

    During normal operation, there are periods of time in which units in a digital system (adders, multipliers etc.) are inactive (i.e. are not processing any useful data). These `latent periods' may be exploited to continually perform sets of unit tests, thus providing a dynamic indication of the healthiness of the system with little or no effect on its performance. The paper details an analysis technique for identifying and quantifying these latent periods by modelling the flow of control through the system as a Markov chain, which takes into account branching and feedback in the controller. The resulting data describes the distribution of latent periods in an entire design, and given a testing requirement in the form of a minimum number of (latent) cycles required to perform a test, provides a figure for how often and to what extent a particular unit may be tested during normal operation. This analysis is utilised to investigate the impact particular optimisation strategies have on the distribution of latent periods, in a number of synthesised benchmark designs. These results are further developed to demonstrate how a knowledge of the latent period distribution can be used to direct the synthesis process and lead to a substantial improvement in the distribution of latent periods, whilst not over adversely affecting other design aspects, particularly the area View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimally distributed computation in augmented networks

    Publication Year: 2000 , Page(s): 27 - 31
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (456 KB)  

    The concept is introduced of `optimally distributed computation' in feedforward neural networks via regularisation of weight saliency. By constraining the relative importance of the parameters, computation can be distributed thinly and evenly throughout the network. It is proposed that this will have beneficial effects on fault-tolerance performance and generalisation ability in augmented network architectures. These theoretical predictions are verified by simulation experiments on two problems; one artificial and the other a `real-world' task. Regularisation terms are presented for distributing neural computation optimally View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Teaching M/G/1 theory with extension to priority queues

    Publication Year: 2000 , Page(s): 23 - 26
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    The derivation of sojourn time distribution is easily understood in M/M/1 queues in terms of numbers of service completions, using the random observer property. The same approach does not generalise directly to the M/G/1 queue because of a subtle dependence between the random variables involved, and an entirely different approach is usually taught in most courses on queueing theory. The M/M/1 approach to the M/G/1 case is applied by accounting for the dependence explicitly. The method then extends simply to M/G/1 queues with priority classes. Although the results themselves are not new, it is believed that the approach used is illuminating, constructive to consistent teaching of the subject and facilitates a concise treatment of priority queues View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • State assignment of finite-state machines

    Publication Year: 2000 , Page(s): 15 - 22
    Cited by:  Patents (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (596 KB)  

    The state assignment problem of finite state machines (FSMs) is addressed. State assignment is a mapping from the set of states (symbolic names) of an FSM to the set of binary codes with the objective of minimising the area of the combinational circuit required to realise the FSM. It is one of the most important optimisation problems in the automatic synthesis of sequential circuits, since it has a major impact on the area, speed, power and testability of the circuits. The problem of finding an optimal state assignment is NP-hard. A new scheme is presented based on mean field annealing (MFA) to solve the graph embedding problem which is the main step in the state assignment process. The MFA algorithm combines the characteristics of simulated annealing and the Hopfield neural network. To solve the problem by MFA, the graph embedding problem is mapped into a neural network and an energy function is formulated. Experiments over the MCNC FSM benchmarks demonstrate that the proposed MFA algorithm can produce superior results, compared with the specialised methods such as the MUSTANG, NOVA and genetic algorithm View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient synthesiser for generation of fast parallel multipliers

    Publication Year: 2000 , Page(s): 49 - 52
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    An automatic generator is developed which can synthesise fixed-point multipliers of any bit accuracy with a speed performance comparable to other recently proposed full-custom results. This synthesiser performs global optimisation for the interconnection of compression elements to minimise the delay in the partial product summation tree (PPST). Also, the final adder following the PPST is carefully synthesised to reduce the cost without sacrificing the speed performance. Unlike the full-custom design method, our synthesiser is adaptable to any technology change. A significant improvement is achieved compared to the Synopsys synthesis results View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault-tolerant wormhole routing algorithm for mesh networks

    Publication Year: 2000 , Page(s): 9 - 14
    Cited by:  Papers (6)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    A multicomputer system can hardly avoid having faulty components in the real world. A good fault-tolerant routing scheme should tolerate as many fault patterns as possible and, hence, reduce the number of disabled functional nodes. The authors consider disconnected unsurrounded faults, i.e. all disconnected faults discussed in the literature. In disconnected unsurrounded fault models, there is no restriction on the shapes of faults. In the proposed routing scheme, a message always leaves each f-ring encountered at an appropriate node such that no message will encounter the same f-ring again and therefore never get trapped in faults View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Asynchronous group mutual exclusion in ring networks

    Publication Year: 2000 , Page(s): 1 - 8
    Cited by:  Papers (7)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    In group mutual exclusion solutions, shared memory models and complete message passing networks have been proposed. These solutions, however, cannot be straightforwardly and efficiently converted to ring networks where each process can only communicate directly with its two neighbouring processes. As rings are also a popular network topology, the paper is focused on ring networks. An efficient and highly concurrent distributed algorithm for the problem is presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.