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IEE Proceedings E - Computers and Digital Techniques

Issue 2 • Mar 1990

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Displaying Results 1 - 9 of 9
  • Automated synthesis of combinational circuits by cascade networks of multiplexers

    Publication Year: 1990, Page(s):164 - 170
    Cited by:  Papers (7)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (412 KB)

    Knowledge of the advantages of realising VLSI circuits in cellular form have stimulated research in the synthesis of digital circuits by using cellular networks of suitable gates. The cascade network is a special kind of cellular form with a very simple interconnection structure. This paper is concerned with the synthesis of combinational circuits using a cascade of 2-input multiplexer units. A mu... View full abstract»

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  • Efficient approach to embed binary trees in 3-D rectangular arrays

    Publication Year: 1990, Page(s):159 - 163
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (280 KB)

    The complete binary tree has long been known to support important applications. This paper presents an efficient embedding of a complete binary tree in a 3-D rectangular array. The array hosting the binary tree is called the host, and the binary tree is referred to as the guest. The scheme is modular and high level trees are made of low level trees inductively. It is shown that all PEs (except one... View full abstract»

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  • Fast transform decoding of nonsystematic Reed-Solomon codes

    Publication Year: 1990, Page(s):139 - 143
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (336 KB)

    By considering a Reed-Solomon (RS) code to be a special case of a redundant residue polynomial code, a fast transform decoding algorithm to correct both errors and erasures is presented. This decoding scheme is an improvement of the decoding algorithm for the redundant residue polynomial code suggested by Shiozaki and Nishida (1975). This decoding scheme can be realised readily on VLSI chips. View full abstract»

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  • Testing of data paths in VLSI arrays

    Publication Year: 1990, Page(s):154 - 158
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (416 KB)

    An important issue in VLSI array design is how to test switches and data links in an array. The authors present a 'divide-and-conquer' technique for testing data paths in VLSI arrays. The data paths including registers, switches and data links are tested in parallel by applying test patterns from the outside. The fault-free paths identified divide the array into smaller subarrays with fault-free b... View full abstract»

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  • Fast algorithms for short prime length fast biased polynomial transforms

    Publication Year: 1990, Page(s):137 - 138
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (132 KB)

    Fast algorithms for three short prime length fast biased polynomial transforms are presented, based on the strategy of the minimum number of rotations. These algorithms are of practical use in digital image processing. View full abstract»

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  • Algorithm for forming relationships between objects in a scene

    Publication Year: 1990, Page(s):151 - 153
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (204 KB)

    An algorithm is described for forming the chaincode and the tree of relationships of the islands and lakes within a bilevel image. View full abstract»

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  • Repairability/unrepairability detection technique for yield enhancement of VLSI memories with redundancy

    Publication Year: 1990, Page(s):133 - 136
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (276 KB)

    In this paper, a new approach to repairability/unrepairability detection for VLSI memory chips with redundancy is presented. An heuristic, yet efficient approach, is proposed. New conditions for detection are presented and fully analysed. These are based on a more accurate estimation of the regions of repairability and unrepairability. The main benefit of this approach is its practicality with res... View full abstract»

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  • Evaluation of real time adaptive noise cancelling algorithms as implemented using a digital signal processor chip

    Publication Year: 1990, Page(s):144 - 150
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (404 KB)

    Adaptive lattice noise cancelling algorithms have features that make them appear attractive for the realisation of realtime adaptive noise cancellers with single chip digital signal processors. Two popular adaptive lattice noise cancelling algorithms have been evaluated for this application. Considered are stochastic gradient lattice and least squares lattice algorithms. For the purpose of compari... View full abstract»

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  • Properties of low augmentation level T-codes

    Publication Year: 1990, Page(s):129 - 132
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (256 KB)

    Initial investigations of the resynchronisation properties of fifth augmentation level, variable length, self-synchronising T-codes are described. It has been found from simulation studies that within the fifth augmentation level family there are considerable differences in the resynchronisation delay statistics of individual code sets, with some code sets consistently out performing others with t... View full abstract»

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