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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 5 • Date May 2000

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Displaying Results 1 - 14 of 14
  • Four-quadrant CMOS current-mode multiplier independent of device parameters

    Publication Year: 2000 , Page(s): 473 - 477
    Cited by:  Papers (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    In this work, we present a four-quadrant CMOS current-mode multiplier based on the square-law characteristics of an MOS transistor operated in the saturation region. One advantage of this multiplier is that the output current is independent of MOS transistor device parameters; another, that the input resistance is independent of the input current. Simulations of the multiplier demonstrate a linearity error of 1.22%, a THD of 1.54%, a -3 dB bandwidth of 22.4 MHz, and a maximum power consumption of 0.93 mW. Operation of the multiplier was also confirmed through an experiment using CMOS 4007 IC's View full abstract»

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  • A novel high-performance CMOS 1-bit full-adder cell

    Publication Year: 2000 , Page(s): 478 - 481
    Cited by:  Papers (40)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    A novel 16-transistor CMOS 1-bit full-adder cell is proposed. It uses the low-power designs of the XOR and XNOR gates, pass transistors, and transmission gates. The cell offers higher speed and lower power consumption than standard implementations of the 1-bit full-adder cell. Eliminating an inverter from the critical path accounts for its high speed, while reducing the number and magnitude of the cell capacitances, in addition to eliminating the short circuit power component, account for its low power consumption. Simulation results comparing the proposed cell to the standard implementations show its superiority. Different circuit structures and input patterns are used for simulation. Energy savings up to 30% are achieved View full abstract»

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  • A folding ADC preprocessing architecture employing a robust symmetrical number system with gray-code properties

    Publication Year: 2000 , Page(s): 462 - 467
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1376 KB)  

    A folding analog-to-digital converter (ADC) preprocessing architecture based on a new robust symmetrical number system (RSNS) is presented. The RSNS preprocessing architecture is a modular scheme in which the integer values within each modulus (comparator states), when considered together, change one at a time at the next position (gray-code properties). Although the observed dynamic range of the RSNS ADC is less than the optimum symmetrical number system ADC, the RSNS gray-code properties make it particularly attractive for error control. With the RSNS preprocessing, the encoding errors due to comparator thresholds not being crossed simultaneously are eliminated. As a result, the interpolation circuits can be removed and only a small number of comparators are required. Computer generated data is used to help determine the properties of the RSNS. These properties include the dynamic range (largest number of distinct consecutive vectors) and the location of the dynamic range within the number system. Closed-form expressions for the dynamic range are also presented for channel moduli of the form m1=2k-1, m2=2k, m3=2k+1. RSNS ADC circuit design principles are presented. To compare the advantages of the RSNS ADC with previously published results, the transfer function of a 3-channel architecture (k=2) is evaluated numerically using SPICE View full abstract»

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  • A low-power orientation-selective vision sensor

    Publication Year: 2000 , Page(s): 435 - 440
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB)  

    We describe the implementation of a focal plane array for computing the outputs of orientation-selective filters similar to Gabor filters using weak inversion transistor circuits. Both the scale and orientation selectivity of the filter can be tuned electronically. We exploit the concept of the transistor as a pseudo-conductance or diffuser and use current, rather than voltage, to represent signals of interest. This design enables energy-efficient computation of the filter responses with similar circuit complexity, as compared with previous strong inversion designs. Test results from a 12×14 pixel array fabricated in 1.2-μm technology are presented View full abstract»

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  • Modeling and optimized design of current mode MUX/XOR and D flip-flop

    Publication Year: 2000 , Page(s): 452 - 461
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    This paper deals with current mode logic (CML) and, in particular, models and optimized design strategies for MUX, XOR, and D flip-flop are presented. Both simple and accurate models for propagation delay are proposed. The models represent propagation delay with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The main difference between accurate and simple models is that the former need only a few SPICE simulations to properly evaluate model parameters. The simple models show errors which are always lower than 20%, while accurate models have typical errors of 2%. Design optimization is in terms of bias currents giving minimum propagation delay, and it has been demonstrated that at the cost of a 10% increase in propagation delay we can reduce power dissipation by 40%. The models and design strategies are validated using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 and 20 GHz, respectively View full abstract»

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  • On parallelism in the ensemble sense between time-series models and discrete wavelet transforms of stochastic signals

    Publication Year: 2000 , Page(s): 485 - 489
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB)  

    The work is concerned with wavelet transforms (WT) of colored (correlated) discrete stochastic signals (time-series) and their relation to AR/ARMA models of the same signals. It derives the relations between AR/ARMA models of WT coefficients and AR/ARMA model of the signal, which eliminates the need to actually perform the WT of such signals in order to derive models of WT coefficients. The work explains how to arrive at the WT coefficient ARMA models from the signal's ARMA model and vice-versa to show that WT properties of the ensemble are fully predictable from the signal's AR/ARMA model. In particular, the authors have shown that from AR/ARMA parameters of the stochastic signal alone, one can derive a realization of the WT coefficients of that stochastic signal and that by invoking the inverse WT on those coefficients, one then retrieves a stochastic signal whose AR/ARMA structure is the same as that of the original signal. It is noted that for a stochastic signal, signal parameters, rather than a particular realization, convey the information on the signal View full abstract»

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  • Effects of transistor nonidealities on high-order log-domain ladder filter frequency responses

    Publication Year: 2000 , Page(s): 373 - 387
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    The nonideality studies on biquadratic log-domain filters are extended to cover high-order filter deviations. It is shown that the log-domain filter nonidealities can be classically understood as integrator magnitude and phase errors, which also bear direct relationship to the component drifts and parasitic dissipations experienced by their passive ancestors. This insight allows us to apply the well-proven LC ladder nonideality theories to our relatively unexplored log-domain regime. We quantify the high-order log-domain filter deviations due to major transistor nonidealities such as parasitic junction resistances, finite beta, and Early effect. SPICE simulations are performed to verify the results. By promoting physical understandings based on the passive ladder, effective and straightforward compensation schemes are proposed View full abstract»

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  • Optimum preamplification and shaping of signals delivered by photodetectors without internal amplification: a theoretical analysis

    Publication Year: 2000 , Page(s): 399 - 407
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    The use of photodetectors without internal amplification is an appealing choice in the design of low-cost solid-state optical instrumentation. However, once photodiodes are used in the detection unit, the instrument sensitivity is related not only to the photodetector characteristics, but mainly to the front-end electronics noise performance. Therefore, great care has to be taken in the design of the preamplification and shaping electronics in order to minimize their noise contribution. The present paper introduces, from the theoretical point of view, the optimum front-end electronics to process signals delivered by photodetectors without internal amplification. In the analysis performed, with simple formalism, the optimum signal-to-noise ratio and the minimum detectable signal have been calculated. Moreover some practical realizations, which approximate the optimum signal processor, are presented View full abstract»

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  • A floating-point processor for fast and accurate sine/cosine evaluation

    Publication Year: 2000 , Page(s): 441 - 451
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    A VLSI architecture for fast and accurate floating-point sine/cosine evaluation is presented, combining floating-point and simple fixed-point arithmetic. The algorithm implemented by the architecture is based on second order polynomial interpolation within an approximation interval which is partitioned into regions of unequal length. The exploitation of certain properties of the trigonometric functions and of specific bit patterns that appear in the involved computations, has led to reduced memory size and low overall hardware complexity. In fact, a 40% memory size reduction is achieved by the introduced simplified memory interleaving scheme, when compared to a traditional interleaved memory architecture. The proposed architecture has been designed and simulated in a 0.7 μm CMOS process technology, to prove its amenability for VLSI implementation. The time required to evaluate a sine is less than the time required for three single-precision floating-point multiply-accumulate (MAC) operations, while the computed values are guaranteed to be accurate to half a unit in last position. To prove the accuracy of the algorithm, an error analysis for the computation of the second-order Horner polynomial is provided, based on novel formulae which have been recently introduced in the literature by the authors for roundoff error bounds in floating-point addition and multiplication View full abstract»

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  • Point-to-point connectivity between neuromorphic chips using address events

    Publication Year: 2000 , Page(s): 416 - 434
    Cited by:  Papers (186)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    This paper discusses connectivity between neuromorphic chips, which use the timing of fixed-height fixed-width pulses to encode information. Address-events (log2(N)-bit packets that uniquely identify one of N neurons) are used to transmit these pulses in real time on a random-access time-multiplexed communication channel. Activity is assumed to consist of neuronal ensembles-spikes clustered in space and in time. This paper quantifies tradeoffs faced in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and concludes that an arbitered channel design is the best choice. The arbitered channel is implemented with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, it is shown how the overhead of arbitrating, and encoding and decoding, can be reduced in area (from N to √N) by organizing neurons into rows and columns, and reduced in time (from log2(N) to 2) by exploiting locality in the arbiter tree and in the row-column architecture, and clustered activity. Throughput is boosted by pipelining and by reading spikes in parallel. Simple techniques that reduce crosstalk in these mixed analog-digital systems are described View full abstract»

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  • Design of simultaneous sampling systems based on fractional delay Lagrange filters

    Publication Year: 2000 , Page(s): 482 - 485
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    Digital filtering is a common approach to achieve simultaneous sampling of several input signals acquired with a multiplexing delay. In this work, an error bound is obtained for Lagrange interpolation filters as a function of the oversampling ratio of the input signals, the fractional delay, and the filter's order. This bound can be used to ensure that the error is small enough to maintain a desired resolution (number of significant bits), thus leading to design equations for simultaneous sampling systems. For example, using these equations, we are able to find that an oversampling ratio of 71 is necessary to maintain a resolution of 12 bits with a first order Lagrange's filter, while a sixth-order filter is required when the oversampling ratio is only five. The theoretical results are validated through simulation, and the computational cost of the Lagrange's interpolator is compared with a polyphase filter View full abstract»

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  • A CMOS general-purpose sampled-data analog processing element

    Publication Year: 2000 , Page(s): 467 - 473
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB)  

    This work presents the architecture and implementation of an analog processor, which in a way akin to a digital microprocessor, embodies a physical model of the universal Turing machine. The analog microprocessor (AμP) executes software programs, while nevertheless operating on analog sampled data values. This enables the design of mixed-mode systems which retain the speed/area/power advantages of the analog signal processing paradigm, while being fully programmable general-purpose systems. A proof-of-concept integrated circuit has been implemented in 0.8-μm CMOS technology, using switched-current techniques. Experimental results from fabricated chips are presented and examples of the application of the AμP's in image processing are given View full abstract»

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  • Digitally programmable decibel-linear CMOS VGA for low-power mixed-signal applications

    Publication Year: 2000 , Page(s): 388 - 398
    Cited by:  Papers (40)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    A new technique for realizing CMOS digitally-controlled decibel-linear variable gain amplifier (VGA) circuits is described. CMOS VGA circuits employing the proposed technique are then given. Besides being effective and simple to use from a system point of view, the VGA circuits offer a stable gain characteristic with precise gain control that is achievable without component spreading. The VGA provides a 25 dB gain control range per stage, with 0.55 dB gain steps and a gain error of less than 0.5 dB. It can also be digitally reconfigured to give a 60 dB gain control range with 6 dB gain steps. The VGA circuit provides digital offset trimming, processes voltage or current input signals and operates in a fully differential configuration. Simulation and experimental results are provided View full abstract»

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  • Adaptive sigma-delta modulation with one-bit quantization

    Publication Year: 2000 , Page(s): 408 - 415
    Cited by:  Papers (16)  |  Patents (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    A method for improving the signal-to-noise ratio (SNR) of sigma-delta modulators with one-bit quantization is presented. The two-level feedback signal of a standard sigma-delta modulator is replaced by a multilevel signal, which is a superposition of two parts. One part s(n) represents a rough estimate of the instantaneous amplitude of the input signal (prediction signal), and the other yb(n) is the sign of the quantizer output, multiplied with constant b. Compared to a nonadaptive modulator, the amplitude of yb(n) is reduced. Therefore, less noise power is introduced in the quantizer, and the SNR is considerably enhanced. Signal s(n) is derived numerically from the quantizer output y0(n) according to a particular adaptation algorithm. Except for the DC-level of s(n), sequence y0 (n) contains the full digital information of the modulator input signal. From y0(n), a digital multilevel sequence w0 (n) can be calculated, which represents the digital modulator output. The price paid for the improved SNR is a moderate slew rate limitation of the input signal. The approach is basically suited for a wide class of sigma-delta modulators. Here, simulation results and an example for a practical implementation of an adaptive sigma-delta modulator of first order are presented View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope