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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 2000

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Displaying Results 1 - 17 of 17
  • Guest editorial

    Publication Year: 2000 , Page(s): 670 - 671
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    Freely Available from IEEE
  • A source-line programming scheme for low-voltage operation NAND flash memories

    Publication Year: 2000 , Page(s): 672 - 681
    Cited by:  Papers (8)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (509 KB)  

    To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 /spl mu/s/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme. View full abstract»

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  • A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming

    Publication Year: 2000 , Page(s): 682 - 690
    Cited by:  Papers (16)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    We report a fast-programming, compact sense and latch (SL) circuit to realize an eight-level NAND flash memory. Fast programming is achieved by supplying optimized voltage and pulsewidth to the bit lines, according to the programming data. As a result, all data programming is completed almost simultaneously, and 0.67-MB/s program throughput, which is 1.7 times faster than conventional program throughput, is achieved. The compact layout of the SL circuit is made possible by four 3-bit latches sharing one unit of the read/verify control circuit. Using these techniques, we fabricated a 144-Mb, eight-level NAND flash memory using a 0.35-/spl mu/m CMOS process, resulting in a 104.2-mm/sup 2/ die size and a 1.05-/spl mu/m/sup 2/ effective cell size. View full abstract»

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  • A robust 8F/sup 2/ ferroelectric RAM cell with depletion device (DeFeRAM)

    Publication Year: 2000 , Page(s): 691 - 696
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (265 KB)  

    This paper describes an area-penalty-free, leakage-compensated, and noise-immune 8F/sup 2/ cell design suitable for high-density, low-power ferroelectric RAM (FeRAM) generations. The new concept features a 1T1C ferroelectric memory cell containing an additional depletion device (DeFeRAM) controlled by the passing word line in a folded bit-line architecture. The depletion device permits the use of a common cell plate at intermediate voltage level. A highly reliable three-level word-line driver circuit design is discussed. View full abstract»

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  • A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme

    Publication Year: 2000 , Page(s): 697 - 704
    Cited by:  Papers (11)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB)  

    This paper presents, for the first time, a 4-Mb ferroelectric random access memory, which has been designed and fabricated with 0.6-/spl mu/m ferroelectric storage cell integrated CMOS technology. In order to achieve a stable cell operation, novel design techniques robust to unstable cell capacitors are proposed: (1) double-pulsed plate read/write-back scheme; (2) complementary data preset reference circuitry; (3) relaxation/fatigue/imprint-free reference voltage generator; (4) open bitline cell array; (5) unintentional power-off data protection scheme. Additionally, to improve cell array layout efficiency a selectively driven cell plate scheme has been devised. The prototype chip incorporating these circuit schemes shows 75 ns access time and 21-mA active current at 3.3 V, 25/spl deg/C, 110-ns minimum cycle. The die size is 116 mm/sup 2/ using 9 /spl mu/m/sup 2/, one-transistor/one-capacitor-based memory cell, twin-well, single-poly, single-tungsten, and double-Al process technology. View full abstract»

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  • Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

    Publication Year: 2000 , Page(s): 705 - 712
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is presented. This redundancy reduces the area required for spare cells from 6 to 1.6% of the area required for normal cells and improves chip yield from 50 to 80%. In addition, it provides a high-speed data path. An embedded DRAM macro adopting the redundancy achieves 200-MHz operation and provides 51.2-Gbit/s bandwidth. It has been fabricated with 0.25-/spl mu/m technology. View full abstract»

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  • A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

    Publication Year: 2000 , Page(s): 713 - 718
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (493 KB)  

    A 7F/sup 2/ DRAM trench cell and corresponding vertically folded bitline (BL) architecture has been fabricated using a 0.175 /spl mu/m technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty-free inter-BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals. A significant improvement of signal margin was measured on a 32-Mbyte test chip. View full abstract»

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  • Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps

    Publication Year: 2000 , Page(s): 719 - 723
    Cited by:  Papers (24)  |  Patents (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (153 KB)  

    A new power saving concept for boosted charge pumps is introduced, that combines two-step adiabatic switching, charge sharing and a simplified clocking scheme to double the power efficiency. Due to the charge charging the clock driver strengths can be reduced and therefore the peak value of the charging current is reduced by a factor of three. Further, the combination of tristate drivers and a new clocking scheme eliminates parasitic charge current peaks and together with the reduced current peaks the electromagnetic emission of the charge pump circuit is reduced significantly. View full abstract»

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  • A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors

    Publication Year: 2000 , Page(s): 724 - 731
    Cited by:  Papers (27)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (521 KB)  

    Novel capacitive fingerprint sensor techniques are described. We propose a novel sensor cell architecture to obtain high sensitivity, wide output dynamic range, and contrast adjustment. For the architecture, three circuit techniques were developed. A sensing circuit with a differential charge-transfer amplifier enhances sensitivity while it suppresses the influence of the parasitic capacitance of the sensor plate. A wide output dynamic range, which is needed for high-resolution analog-to-digital (A/D) conversion, is achieved by transforming the sensed voltage to a time-variant signal. Finally, the sensing circuit includes an automatic contrast enhancement scheme that uses a variable-threshold Schmitt trigger circuit to distinguish the ridges and valleys of a fingerprint well. The characteristics of a test chip using the 0.5-/spl mu/m CMOS process show a high sensitivity to less than 80 fF as the detected signal, while the variation of the output signal is suppressed to less than 3% at /spl plusmn/20% variation of the parasitic capacitance. The dynamic range of the time-variant signal is 70 /spl mu/s, which is wide enough for A/D conversion. The automatic contrast enhancement scheme widens the time-variant signal 100 /spl mu/s more. A single-chip fingerprint sensor/identifier LSI using the proposed sensing circuit scheme confirms the scheme's effectiveness. View full abstract»

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  • 100000-pixel, 120-dB imager in TFA technology

    Publication Year: 2000 , Page(s): 732 - 739
    Cited by:  Papers (18)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1254 KB)  

    A locally autoadaptive image sensor LARS II (Lokal-AutoadaptiveR Sensor) with 368/spl times/256 pixels was designed and fabricated in thin film on ASIC (TFA) technology. Every pixel contains an automatic shutter, made of 17 transistors and two capacitors on an area of 40/spl times/38.3 /spl mu/m/sup 2/, that adapts the integration time to the local intensity. This allows the capture and processing of scenes with extremely high dynamic range. For the amorphous detector system, local contrast and temperature stability are demonstrated to be excellent while the transient response is sufficient for imaging applications. Sample images shown in this paper verify the total dynamic range of 120 dB. View full abstract»

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  • A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization

    Publication Year: 2000 , Page(s): 740 - 750
    Cited by:  Papers (42)
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    This work describes the implementation of a discrete cosine transform (DCT) core compression system targetted to low-power video (MPEG2 MP@ML) and still-image (JPEG) applications. It exhibits two innovative techniques for arithmetic operation reduction in the DCT computation context along with standard voltage scaling techniques such as pipelining and parallelism. The first method dynamically minimizes the bitwidth of arithmetic operations in the presence of data spatial correlation. The second method trades off power dissipation and image compression quality (arithmetic precision). The chip dissipates 4.38 mW at 14 MHz and 1.56 V. View full abstract»

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  • A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 /spl mu/m SOI-CMOS technology

    Publication Year: 2000 , Page(s): 751 - 756
    Cited by:  Papers (3)  |  Patents (5)
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    This paper describes a 16:1 multiplexer using 0.18 /spl mu/m SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers. View full abstract»

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  • A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver

    Publication Year: 2000 , Page(s): 757 - 764
    Cited by:  Papers (81)  |  Patents (45)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50/spl deg/, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2/spl times/2 mm/sup 2/ chip consumes 1.1 W at 8 Gb/s with a 3-V supply. View full abstract»

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  • A 5-GHz CMOS wireless LAN receiver front end

    Publication Year: 2000 , Page(s): 765 - 772
    Cited by:  Papers (110)  |  Patents (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (230 KB)  

    This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-/spl mu/m CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm. View full abstract»

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  • A wide tuning range gated varactor

    Publication Year: 2000 , Page(s): 773 - 779
    Cited by:  Papers (17)  |  Patents (23)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (433 KB)  

    A wide tuning range gated varactor for radio frequency (RF) applications is described in this paper. The gated varactor is a three-terminal device. The third terminal helps achieve an improved tuning range. The measured tuning range of the varactor exceeds /spl plusmn/50%. The new device can be implemented with a standard CMOS process without any post-processing. A 2 GHz prototype voltage-controlled oscillator (VCO) is implemented using the new varactor in a 0.35-/spl mu/m CMOS process. The VCO achieved a sensitivity of 220 MHz/V. View full abstract»

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  • A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver

    Publication Year: 2000 , Page(s): 780 - 787
    Cited by:  Papers (92)  |  Patents (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (289 KB)  

    A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 /spl mu/m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc. View full abstract»

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  • A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m CMOS technology

    Publication Year: 2000 , Page(s): 788 - 794
    Cited by:  Papers (60)  |  Patents (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (199 KB)  

    This paper describes the design of a CMOS frequency synthesizer targeting wireless local-area network applications in the 5-GHz range. Based on an integer-N architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the circuit provides a channel spacing of 23.5 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBc/Hz at 2.6 GHz and -100 dBc/Hz at 5.2 GHz (both at 10-MHz offset). The reference sidebands are at -53 dBc at 2.6 GHz, and the power dissipation from a 2.6-V supply is 47 mW. View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan