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Electron Devices, IEEE Transactions on

Issue 5 • Date May 2000

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Displaying Results 1 - 25 of 33
  • A strategy for modeling of variations due to grain size in polycrystalline thin-film transistors

    Publication Year: 2000 , Page(s): 1035 - 1043
    Cited by:  Papers (33)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    A strategy is presented for modeling of performance variation in polycrystalline thin-film transistors (TFT's) due to grain size variation. A Poisson area scatter is used to model the number of grains in a TFT, which is converted to grain size and substituted into physically based models for threshold and mobility. An increase in device variation is predicted as the device and grain sizes converge through scaling or process changes. Comparison of the model with measurements of NMOS TFT's results in reasonable agreement View full abstract»

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  • Fabrication of strained and double heterojunction InxGa 1-xP/In0.2Ga0.8As high electron mobility transistors grown by solid-source molecular beam epitaxy

    Publication Year: 2000 , Page(s): 1115 - 1117
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    Double heterojunction (DH) In0.48Ga0.52P/In 0.20Ga0.80As and strained single heterojunction (SSH) In0.40Ga0.60P/In0.20Ga0.80 As/GaAs high electron mobility transistor (HEMT) structures were grown by solid-source molecular beam epitaxy (SSMBE) using a valved phosphorus cracker cell. The DC and RF performance of the SSH-HEMT and DH-HEMT were compared with the single heterojunction (SH) HEMT. The results show a significant improvement in device characteristics in the SSH-HEMT with In0.40Ga0.60P spacer and Schottky layer, due to better carrier confinement in the channel. The SSH-HEMT with 0.35-μm gate length exhibits a peak transconductance (Gm ) of 470 mS/mm, maximum drain current (IDSmax) of 550 mA/mm, and current gain cut-off frequency (fT) of 50 GHz. These values are approximately 7%, 10% and 25% higher than the respective values for a DH-HEMT of identical gate length View full abstract»

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  • A better insight into the performance of silicon BJTs featuring highly nonuniform collector doping profiles

    Publication Year: 2000 , Page(s): 1044 - 1051
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    This paper investigates the effects of highly nonuniform collector doping profiles on the speed and breakdown performance of silicon bipolar transistors. Monte Carlo and drift diffusion simulation results point out that a thin highly doped layer adjacent to the base collector junction can improve the device cut off frequency without deteriorating significantly the maximum oscillation frequency and the breakdown voltage, provided the voltage drop across this layer is lower than an effective threshold of approximately 1.2 V. Guidelines are given for choosing the doping, position, and thickness of this layer View full abstract»

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  • Avalanche noise characteristics of thin GaAs structures with distributed carrier generation [APDs]

    Publication Year: 2000 , Page(s): 910 - 914
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    It is known that both pure electron and pure hole injection into thin GaAs multiplication regions gives rise to avalanche multiplication with noise lower than predicted by the local noise model. In this paper, it is shown that the noise from multiplication initiated by carriers generated throughout a 0.1 μm avalanche region is also lower than predicted by the local model but higher than that obtained with pure injection of either carrier type. This behavior is due to the effects of nonlocal ionization brought about by the dead space; the minimum distance a carrier has to travel in the electric field to initiate an ionization event View full abstract»

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  • An analytical model for breakdown voltage of surface implanted SOI RESURF LDMOS

    Publication Year: 2000 , Page(s): 1006 - 1009
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    An analytical model for the breakdown voltage of the surface implanted silicon-on-insulator (SOI) REduced SURface Field (RESURP) LDMOS is presented, which allows useful design curves of breakdown voltage in terms of the device parameters, including the substrate bias voltage. Improvement on both the breakdown voltage and the on-resistance of the device due to the surface implantation is demonstrated. Numerical simulations are shown to support the analytical results View full abstract»

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  • RF performance degradation in nMOS transistors due to hot carrier effects

    Publication Year: 2000 , Page(s): 1068 - 1072
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    This paper reports the hot electron induced RF performance degradation in multifinger gate nMOS transistors within the general framework of the degradation mechanism. The RF performance degradation of hot-carrier stressed nMOS transistors can be explained by the transconductance degradation, which resulted from the interface state generation. It has been found that the RF performance degradation, especially minimum noise figure degradation, is more significant than dc performance degradation. From the experimental correlation between RF and dc performance degradation, RF performance degradation can be predicted just by the measurement of dc performance degradation or the initial substrate current. From our experimental results, hot electron induced RF performance degradation should be taken into consideration in the design of the CMOS RF integrated circuits View full abstract»

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  • Hot-carrier degradation behavior of thin-film SOI nMOSFET with isolation scheme and buried oxide thickness

    Publication Year: 2000 , Page(s): 1013 - 1017
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    Hot-carrier degradation behavior of thin-film SOI (silicon-on-insulator) nMOSFETs with various isolation techniques and buried oxide (BOX) thickness has been investigated focused on the stress behavior in the SOI structure. LOCOS (local oxidation of silicon) and STI (shallow trench isolation) processes are used as isolation techniques. Buried oxide thickness is 100 and 400 nm, respectively. From the isolation point of view, STI-processed SOI devices have better hot-carrier immunity than LOCOS-isolated SOI devices. In terms of BOX thickness, the thick BOX case has better hot-carrier degradation characteristics than the thin one. It is found that STI process and thick BOX cases induce smaller stress than LOCOS process and thin BOX cases, resulting in better hot-carrier immunity View full abstract»

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  • Design and characterization of superlattice infrared photodetector operating at low bias voltage

    Publication Year: 2000 , Page(s): 944 - 948
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (132 KB)  

    In this paper, we investigate the performance and characterization of a 15-period superlattice embedded between two thick AlGaAs barriers. The structure can operate at low bias voltage with less power consumption for 8-10 μm long-wavelength infrared detection. In our design, one barrier is used to reduce the dark current and the other one is designed to enhance the collection efficiency of photoelectrons at the collector contact. The fabricated detector can be operated at a bias voltage lower than 0.1 V and exhibits a pronounced photovoltaic response. The spectral response shows voltage dependence around 0 V. At high bias voltage (>25 mV) the spectral lineshape is independent of bias and is around 8-10 μm with peak wavelength at 9.3 μm. At lower bias voltage the response is shifted toward shorter wavelength range. The peak responsivity was found to be 12 mA/W at λp =8.7 μm and zero bias and 85 mA/W at λp=9.3 μm and 0.1 V. Background limitation can be achieved up to 65 K with bias voltage less than 0.1 V. The measured noise power spectral density of the dark current at 77 K shows the characteristics of full shot noise rather than generation-recombination noise. The peak detectivity is determined to be D*=3.5×109 cm√(Hz)/W at 77 K and 0.1 V. In comparison with a conventional 30-period QWIP, our detector has the advantages of better performance at low bias voltages with lower power consumption and a tunable feature of spectral range View full abstract»

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  • On the origin of the dispersion of erased threshold voltages in flash EEPROM memory cells

    Publication Year: 2000 , Page(s): 1120 - 1123
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    This work investigates the origin of the dispersion of tunnel-erased threshold voltages (VT) in flash EEPROM memory cells. A clear correlation between cell-to-cell variations of tunnel current IT and dispersion of erased VT is demonstrated by looking at the IT characteristics and the erasing characteristics corresponding to channel and source injection as well as at the dependence of IT and VT dispersion on device area and tunnel polarity. Experimental evidence is provided that nonuniform injection at poly-Si/SiO2 interface is a major cause of erased VT dispersion View full abstract»

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  • A new quantum effect model for practical device simulation

    Publication Year: 2000 , Page(s): 1010 - 1012
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB)  

    An increase in the complexity of VLSI design, especially in process integration, is leading to increased demands for technology CAD (TCAD). The quantum mechanical (QM) effect becomes very important with an increase in the channel impurity concentration. Several models for the QM effect have been proposed. However, it has been reported that these models had some problems. In this paper, a new QM model for a conventional device simulator is proposed. Applications of this model to NMOS and PMOS including the buried-channel are examined View full abstract»

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  • The effect of Co incorporation on electrical characteristics of n +/p shallow junction formed by dopant implantation into CoSi 2 and anneal

    Publication Year: 2000 , Page(s): 994 - 998
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    The impact of Co incorporation on the electrical characteristics has been investigated in n+/p junction formed by dopant implantation into CoSi2 and drive-in anneal. The junctions were formed by As+ (30 or 40 keV, 1×1016 cm -2) implantation into 35 nm-thick CoSi2 followed by drive-in annealing at 900°C for 30 s in an N2 ambient. Deeper junction implanted by As+ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As + at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi2 layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps View full abstract»

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  • Temperature dependence and electrical properties of dominant low-frequency noise source in SiGe HBT

    Publication Year: 2000 , Page(s): 1107 - 1112
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    The temperature dependence and electrical properties of the dominant low-frequency noise source in a SiGe HBT have been investigated. By employing a temperature variation of the device to get a variation of the base or collector current independently of each other, it is shown that the dominant noise source is strongly dependent on the collector current, but only weakly dependent on the base current. A modified Ebers-Moll model is presented that accounts for the collector current dependence of the dominant noise source and simultaneously accounts for the temperature dependence of β. Using the modified Ebers-Moll model, the understanding of the physical positioning of the noise source is simplified View full abstract»

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  • The merits and limitations of local impact ionization theory [APDs]

    Publication Year: 2000 , Page(s): 1080 - 1088
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    Multiplication measurements on GaAs p+-i-n+s with i-region thicknesses, w, between 1 μm and 0.025 μm and Monte Carlo (MC) calculations of the avalanche process are used to investigate the applicability of the local ionization theory. The local expressions for multiplication are able to predict the measured values surprisingly well in p+-i-n+s with i-region thicknesses, w, as thin as 0.2 μm before the effect of dead-space, where carriers have insufficient energy to ionize, causes significant errors. Moreover, only a very simple correction to the local expressions is needed to predict the multiplication accurately where the field varies rapidly in abrupt one-sided p+-n junctions doped up to 1018 cm-3. However, MC modeling also shows that complex dead-space effects cause the local ionization coefficients to be increasingly unrepresentative of the position dependent values in the device as w is reduced below 1 μm. The success of the local model in predicting multiplication is therefore attributed to the dead-space information already being contained within the experimentally determined values of local coefficients. It is suggested that these should therefore be thought of as effective coefficients which, despite the presence of dead-space effects, can be still be used with the existing local theory for efficiently quantifying multiplication and breakdown voltages View full abstract»

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  • Numerical modeling of energy balance equations in quantum well Al xGa1-xAs/GaAs p-i-n photodiodes

    Publication Year: 2000 , Page(s): 915 - 921
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    The energy balance equations coupled with drift diffusion transport equations in heterojunction semiconductor devices are solved modeling hot electron effects in single quantum well p-i-n photodiodes. The transports across the heterojunction boundary and through quantum wells are modeled by thermionic emission theory. The simulation and experimental current-voltage characteristics of a single p-i-n GaAs/Al xGa1-xAs quantum well agree over a wide range of current and voltage, The GaAs/AlxGa1-xAs p-i-n structures with multi quantum wells are simulated and the dark current voltage characteristics, short circuit current, and open circuit voltage results are compared with the available experimental data, In agreement with the experimental data, simulated results show that by adding GaAs quantum wells to the conventional cell made of wider bandgap Alx Ga1-xAs, short circuit current is improved, but there is a loss of the voltage of the host cell, In the limit of radiative recombination, the maximum power point of an Al0.35Ga0.65As/GaAs p-i-n photodiode with 30-quantum-well periods is higher than the maximum power point of similar conventional bulk p-i-n cells made out of either host Al0.35Ga0.65As or bulk GaAs material View full abstract»

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  • An analytic model for estimating the length of the velocity saturated region in GaAs MESFETs

    Publication Year: 2000 , Page(s): 905 - 909
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    An analytical model is presented for estimating the length of the portion of an FET channel with velocity saturated carriers. The model is based on previous work proposed by Pucel et al. [1974, 1975], and has been adapted to remove discontinuities between extreme bias conditions. The need for complicated numerical solutions has also been removed making the model suitable for use with circuit simulators. Results obtained from the model agree well with previously proposed models over a wide range of bias conditions where velocity saturation can be either dominant or negligible, depending on the overall channel length and bias conditions View full abstract»

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  • Characterization of the MIC/MILC interface and its effects on the performance of MILC thin-film transistors

    Publication Year: 2000 , Page(s): 1061 - 1067
    Cited by:  Papers (60)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    Process and material characterization of the crystallization of amorphous silicon by metal-induced crystallization (MIC) and metal-induced lateral crystallization (MILC) using evaporated Ni has been performed. An activation energy of about 2 eV has been obtained for the MILC rate. The Ni content in the MILC area is about 0.02 atomic %, significantly higher than the solid solubility limit of Ni in crystalline Si at the crystallization temperature of 500°C. A prominent Ni peak has been detected at the MILC front using scanning secondary ion mass spectrometry. The MIC/MILC interface has been determined to be highly defective, comprising a continuous grain boundary with high Ni concentration. The effects of the relative locations of this interface and the metallurgical junctions on TFT performance have been studied View full abstract»

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  • A physical model for the kink effect in InAlAs/InGaAs HEMTs

    Publication Year: 2000 , Page(s): 922 - 930
    Cited by:  Papers (41)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    We present a new model for the the kink effect in InAlAs/InGaAs HEMTs. The model suggests that the kink is due to a threshold voltage shift which arises from a hole pile-up in the extrinsic source and an ensuing charging of the surface and/or the buffer-substrate interface. The model captures many of the observed behaviors of the kink, including the kink's dependence on bias, time, temperature, illumination, and device structure. Using the model, we have developed a simple equivalent circuit, which reproduced well the kink's dc characteristics, its time evolution in the nanosecond range, and its dependence on illumination View full abstract»

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  • High performance damascene metal gate MOSFETs for 0.1 μm regime

    Publication Year: 2000 , Page(s): 1028 - 1034
    Cited by:  Papers (17)  |  Patents (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (532 KB)  

    A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO2 or Ta2O5 as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance View full abstract»

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  • Coupled drift-diffusion/quantum transmitting boundary method simulations of thin oxide devices with specific application to a silicon based tunnel switch diode

    Publication Year: 2000 , Page(s): 1052 - 1060
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    We present a method of coupling drift-diffusion simulations with quantum transmitting boundary method (QTBM) tunnel current calculations. This allows self-consistent simulation of thin oxide devices in which large tunnel currents can flow. Simulated results are presented for a thin oxide Al/SiO2/Si structure and an Al/SiO2/n-Si/p-Si tunnel switching diode. We demonstrate the careful use of the recombination lifetime as an adjustable or relaxable parameter in order to obtain converging solutions View full abstract»

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  • Impact of electron and hole inversion-layer capacitance on low voltage operation of scaled n- and p-MOSFET's

    Publication Year: 2000 , Page(s): 999 - 1005
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    The influence of inversion-layer capacitance (Cinv) on supply voltage (Vdd) of n- and p-MOSFET's is quantitatively examined. The physical origin of the effect of Cinv on Vdd consists in the band bending of a Si substrate in the inversion condition due to Cinv, which is not scaled with a reduction in gate oxide thickness. The amount and the impact of the band bending is accurately evaluated on a basis of one dimensional (1-D) self-consistent calculations including two-dimensional (2-D) subband structure of inversion-layer electrons and holes. It is demonstrated that additional band bending of a Si substrate due to Cinv becomes a dominant factor to limit the lowering of Vdd for CMOS with ultrathin gate oxides. The operation at Vdd lower than 0.6 V is quite difficult even with effective Tox less than 1 nm View full abstract»

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  • An a-SiGe:H phototransistor integrated with a Pd film on glass substrate for hydrogen monitoring

    Publication Year: 2000 , Page(s): 939 - 943
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    A novel a-SiGe:H optoelectronic hydrogen gas sensing device has been developed. The optoelectronic gas sensing device integrated a high optical gain a-SiGe:H optical sensor with a sputtered palladium (Pd) film on a glass substrate. Through the mechanism of the Pd film's transmitted optical power modulated with the H2 concentration in atmosphere, the device can be operated at room temperature with a wider range (50 ppm to 133000 ppm) and faster response, in comparison to a conventional Pd catalytic type H2 sensors, thus providing a good candidate for hydrogen monitoring View full abstract»

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  • On the behaviour of p-n junction solar cells made in fine-grained silicon layers

    Publication Year: 2000 , Page(s): 1118 - 1120
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (84 KB)  

    The behavior of polycrystalline p-n-junction solar cells with a grain size in the order of 1 μm is investigated. The diffusion length appears larger than the average grain size at low doping levels but drastically decreases with increasing doping level, with moderate improvement through hydrogenation. The second diode currents are generally very large, leading to poor open-circuit voltages. We suggest that the zone of enhanced recombination, usually confined to the junction depletion region, extends into the base where very small grains are completely depleted due to carrier trapping at grain boundaries View full abstract»

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  • On-chip characterization of interconnect parameters and time delay in 0.18 μm CMOS technology for ULSI circuit applications

    Publication Year: 2000 , Page(s): 1073 - 1079
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    A real time, on-chip characterization technique is presented for extracting the interconnect parameters and for determining the associated time delays for ULSI circuit applications. To demonstrate the method, test chips were fabricated in both 0.25 and 0.18 μm CMOS technologies, using state of the art process technologies. Results obtained in these two cases are compared and the changing trends and issues for interconnect parameters in making the transition from the 0.25 μm to the 0.18 μm technologies are discussed. A completed look-up table in conjunction with a working analytic expression of the time delay enables accurate modeling and optimization of interconnect parameters and time delays for a given specification of chip performance View full abstract»

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  • A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications

    Publication Year: 2000 , Page(s): 1018 - 1027
    Cited by:  Papers (66)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    The pseudo-MOS transistor (Ψ-MOSFET) is a surprising and useful technique for the rapid evaluation of SOI wafers, prior to any CMOS processing. We review the static and dynamic modes of operation as well as the main models and methods for electrical parameter extraction. Selected numerical simulations are presented in order to clarify the optimal conditions of operation. Finally, practical applications are exemplified which illustrate the efficiency of the Ψ-MOSFET technique for in situ characterization of SOI technologies and processes View full abstract»

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  • Comprehensive study of rapid, low-cost silicon surface passivation technologies

    Publication Year: 2000 , Page(s): 987 - 993
    Cited by:  Papers (28)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    A comprehensive and systematic investigation of low-cost surface passivation technologies is presented for achieving high-performance silicon devices such as solar cells. Most commercial solar cells today lack adequate surface passivation, while laboratory cells use conventional furnace oxides (CFO) for high-quality surface passivation involving an expensive and lengthy high-temperature step. This investigation tries to bridge the gap between commercial and laboratory cells by providing fast, low-cost methods for effective surface passivation. This paper demonstrates for the first time, the efficacy of TiO2, thin (<10 nm) rapid thermal oxide (RTO), and PECVD SiN individually and in combination for (phosphorus diffused) emitter and (undiffused) back surface passivation. The effects of emitter sheet resistance, surface texture, and three different SiN depositions (two direct PECVD systems and one remote plasma system) were investigated. The effects of post-growth/deposition treatments such as forming gas anneal (FGA) and firing of screen printed contacts were also examined. This study reveals that the optimum passivation scheme consisting of a thin RTO with a SiN cap followed by a very short 730°C anneal can 1) reduce the emitter saturation current density, J0e, by a factor of >15 for a 90 Ω/sq. emitter, 2) reduce J0e by a factor of >3 for a 40 Ω/sq, emitter, and 3) reduce Sback below 20 cm/s on 1.3 Ωcm p-Si. Furthermore, this double-layer RTO+SiN passivation is relatively independent of the deposition conditions (direct or remote) of the SiN film and is more stable under heat treatment than SiN or RTO alone. Model calculations are also performed to show that the RTO+SiN surface passivation scheme may lead to 17%-efficient thin screen-printed cells even with a low bulk lifetime of 20 μs View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego