Issue 4 • Date April 2000
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Displaying Results 1 - 15 of 15
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Comments on "A systematic approach for design of digit-serial signal processing architectures"
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PDF (109 KB)
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MVDR beamforming and generalized sidelobe cancellation based on inverse updating with residual extraction
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PDF (428 KB)
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Generating nearly optimally compact models from Krylov-subspace based reduced-order models
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PDF (368 KB)
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Computer-aided circuit analysis tools for RFIC simulation: algorithms, features, and limitations
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PDF (240 KB)
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Synthesis of time-domain models for interconnects having 3-D structure based on FDTD method
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PDF (148 KB)
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A continuous-time common-mode feedback circuit (CMFB) for high-impedance current-mode applications
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PDF (280 KB)
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Extended mean-distance-ordered search using multiple l1 and l2 inequalities for fast vector quantization
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PDF (200 KB)
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A method for reduced-order modeling and simulation of large interconnect circuits and its application to PEEC models with retardation
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PDF (400 KB)
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Aims & Scope
The latest title for this publication is IEEE Transactions on Circuits and Systems I: Regular Papers.


