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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 4 • Date Apr 2000

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Displaying Results 1 - 9 of 9
  • Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model

    Page(s): 446 - 458
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    To improve the performance of critical nets where both timing and wire resources are stringent, we integrate buffer insertion and driver sizing separately with non-Hanan optimization and propose two algorithms: simultaneous buffer insertion and non-Hanan optimization (BINO) and full-plane AWE routing with driver sizing (FAR-DS). For BINO, we consider the realistic situation that buffer locations are restricted to a limited set of available spaces after cell placement. The objective of BINO is to minimize a weighted sum of wire and buffer costs subject to timing constraints. To achieve this objective, we suggest a greedy algorithm that considers two operations independently: iterative buffer insertion and iterative buffer deletion. Both are conducted simultaneously with non-Hanan optimization until the improvement is exhausted. For FAR-DS, we investigate the curvature property of the sink delay as a function of both connection location and driver stage ratio in a two-dimensional (2-D) space. The objective of FAR-DS is to minimize a weighted sum of wire and driver cost while ensuring that the timing constraints are satisfied. Based on the curvature property, we search for the optimal solution in the continuous 2-D space. In both BINO and FAR-DS, a fourth-order AWE delay model is employed to assure the quality of optimization. Experiments of BINO and FAR-DS on both integrated circuit and MCM technologies showed significant cost reductions compared with SERT and MVERT in addition to making the interconnect to satisfy timing constraints View full abstract»

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  • Bridge fault diagnosis using stuck-at fault simulation

    Page(s): 489 - 495
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    A new diagnostic fault simulator is described that diagnoses both feedback and nonfeedback bridge faults in combinational circuits while using information from fault simulation of single stuck-at faults. A realistic fault model is used which considers the existence of the Byzantine Generals problem. Sets representing nodes possibly involved in a defect are partitioned based on logic and fault simulation of failing vectors. The approach has been demonstrated for two-line bridge faults on several large combinational benchmark circuits containing Boolean primitives and has achieved over 98% accuracy for nonfeedback bridge faults and over 85% accuracy for feedback bridge faults with good diagnostic resolution View full abstract»

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  • Time-domain thermal noise simulation of switched capacitor circuits and delta-sigma modulators

    Page(s): 473 - 481
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    This paper presents an accurate and efficient algorithm for simulating the effects of thermal noise in time-domain. The algorithm presented in this paper is based on Monte Carlo methods and is applicable to linear time invariant circuits. In addition to linear time invariant elements, the algorithm can easily be extended to include clock controlled switches and single or multibit quantizers. This expands the thermal noise analysis capability to switched capacitor circuits and oversampled delta-sigma modulators. Thermal noise generated by different elements is modeled, in the time-domain, by a random pulse waveform having a desired power spectral density. Typically the noise power level is much smaller than that of other desired signals in the circuit and accurate simulation is needed to obtain correct results. In addition, random noise waveforms require the computation of many time points in each transient analysis and efficient simulation methods are needed. In this paper, a new method for computing the transient response of linear time invariant circuits is used. This method accurately and efficiently computes the response to the random pulse waveforms. In addition to thermal noise, the method can also be used to simulate the effect of random dither signals in delta-sigma modulators. Examples of noise simulation are given and, when possible, comparison with measurements, previously published results, or analytical expressions is done View full abstract»

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  • Automated synthesis of current-memory cells

    Page(s): 413 - 424
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    The switched current circuit technique allows mixed-signal integrated circuits including data-converters and filters to be fabricated in a conventional CMOS process. ASIMOV, described in this paper, is a computer-aided design tool to support the systematic design of such circuits. It is capable of topology selection and sizing of current memory cells from a set of user specifications, Analytical models, coupled with numerical optimization guided by a heuristic rule-base, are used for fast response time. Models for the most commonly used cells are implemented View full abstract»

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  • A multilevel engine for fast power simulation of realistic input streams

    Page(s): 459 - 472
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    Power estimation for validation and sign-off is a critical step in the design process. In this phase, accuracy is a key requirement, but there are hard constraints on the time that can be dedicated to power estimation. Moreover, it is important to estimate the power dissipated by the system while running typical applications, i.e., extremely long streams of validation patterns provided by the designer. The power dissipated by digital systems under realistic input stimuli is not accurately described by a single average value, but by a waveform that shows how power consumption varies over time as the system responds to the inputs. In this paper, we face the problem of obtaining accurate power waveforms for combinational and sequential circuits under typical usage patterns. We propose a multilevel simulation engine that achieves high accuracy in estimating the time-domain power waveform, as well as the average power with high computational efficiency View full abstract»

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  • Integrated parametric timing optimization of digital systems

    Page(s): 482 - 489
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    Clock skew optimization is a timing technique to improve system performance by employing scheduled skews at flip-flops. The integrated framework presented here includes a new linear programming (LP) formulation for the clock skew optimization problem. In this work, we use the concept of a global time frame, instead of a local one, to find a set of optimal skews to minimize system cycle time. The framework provides a firm theoretical foundation for scheduling skews into existing designs. Furthermore, we extend the LP formulation to accommodate retiming in the optimization process. Our framework allows for concurrent timing optimization of a design by retiming the circuit and scheduling clock skews at flip-flops. It is shown that this optimization can be formulated as a mixed-integer linear program and significantly reduce the clock period View full abstract»

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  • Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams

    Page(s): 401 - 412
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    A new method is proposed for hierarchical symbolic analysis of large analog integrated circuits. It consists of performing symbolic suppression of each subcircuit to its terminals in terms of subcircuit matrix determinants and cofactors, and applying Cramer's rule to symbolically solve the set of equations at the top level of the circuit hierarchy. An annotated, directed, and acyclic graph, called determinant decision diagram (DDD), is used to represent symbolic determinants of subcircuit matrices and cofactors used in subcircuit suppression, as well as symbolic determinants of the top-level circuit matrix and cofactors required in applying Cramer's rule. DDD enables us to systematically exploit the inherent sparsity of circuit matrices and the sharing of symbolic expressions. It is capable of representing a huge number of symbolic product terms in a canonical and highly compact manner. The proposed method is illustrated using a Cauer parameter low-pass filter. It has been implemented in a symbolic analyzer and compared to best-known hierarchical symbolic analyzer SCAPP and numerical simulator SPICE. Experimental results on several analog circuits including the μA741 operational amplifier - a circuit with less structural regularities - are described View full abstract»

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  • Intrinsic response extraction for the removal of the parasitic effects in analog test buses

    Page(s): 437 - 445
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    The removal of the parasitic effects is an emerging issue in the implementation of the IEEE standard 1149.4 analog test buses. For this, this paper defines the intrinsic response and derives an extraction algorithm. The intrinsic response is defined as the response of the circuit being tested by an ideal input signal without the parasitic effect. A deconvolution process is proposed to extract the intrinsic response from the response contaminated by the parasitic effects. The test results using SPICE simulation data show that the intrinsic responses remain the same regardless of the differences in the parasitic effects and the variations in the test signals. The proposed methodology is further tested in the real measurement using the MNABST-1 test chip designed by Matsushita/Panasonic and provided by 1149.4 Working Group. The test results show that the intrinsic response has an improvement of 15.4 dB in signal-to-noise ratio as compared to the direct measurement. It also extends the test frequency range by an order of magnitude. Both tests reassert that the intrinsic response is independent of parasitic effects and input signal variation. They also show that the proposed extraction algorithm is robust enough to handle not only the parasitic effects but also the noise in the real measurement environment View full abstract»

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  • Return-limited inductances: a practical approach to on-chip inductance extraction

    Page(s): 425 - 436
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    Decreasing slew rates and efforts to reduce the resistance-capacitance (RC) delays of on-chip interconnect through design and technology have resulted in the growing importance of inductance in analyzing interconnect response for timing and noise analysis. In this paper, we consider a practical approach for extracting approximate inductances of on-chip interconnect. This approach, which we call the method of return-limited inductances, is based on performing the inductance modeling of signal lines and power-ground lines independently and on taking advantage of the power and ground distribution of the chip to localize inductive coupling. A set of simple geometry-based matrix decomposition rules guide sparsification in these extractions View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu