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Computers and Digital Techniques, IEE Proceedings -

Issue 6 • Date Nov. 1999

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Displaying Results 1 - 6 of 6
  • ETDD-based synthesis of two-dimensional cellular arrays for multi-output incompletely specified Boolean functions

    Publication Year: 1999 , Page(s): 302 - 308
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    Complex terms are logic expressions which can be mapped directly to cell arrays of cellular architecture devices such as Atmel 6000 series FPGAs. The paper presents an approach to the generation of complex terms for multi-output incompletely specified Boolean functions using EXOR ternary decision diagrams ETDDs. The expansions, Shannon, positive Davio and negative Davio, inherent in ETDDs, are employed to generate complex terms. While traversing the ETDD can be accomplished in a simple and efficient way for completely specified functions, the manipulation of ETDDs with don't care terms becomes very complex because the three expansions require different evaluations of the function. The changes made to the function due to don't cares in each expansion are analysed, and an approximation algorithm is presented with its applications to the minimisation of functions composed of complex terms. View full abstract»

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  • Efficient conversion algorithms for long-word-length binary logarithmic numbers and logic implementation

    Publication Year: 1999 , Page(s): 295 - 301
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (548 KB)  

    The logarithmic number system is an attractive alternative to the conventional number systems when data need to be manipulated at very high rate over a wide data range. However, the major problem is deriving logarithms and antilogarithms quickly and accurately enough to allow conversions to and from the conventional number representations. The paper presents efficient algorithms that convert the conventional binary numbers to binary logarithmic numbers, where long-word-length numbers are considered. The conversion problem can be formulated as a division-like problem. This implementation adopts the modified SRT division scheme so that the full-length addition/subtraction operations can be avoided. The speed performance of the logic implementation has been evaluated based on the TSMC 0.8 μm SPDM CMOS process. Results show that, for the numbers in IEEE double precision format with 53 bits in the fractional part and with an additional seven guarding digits to maintain the accuracy, it takes about 0.4 μs to convert a number, where the ROM table size is 128-by-60 bits, or 7.5 kbits. The speed performances of the logic implementation for long-word-length, such as 128 bits, 256 bits, and 512 bits, are also evaluated in terms of the required ROM table size and delay time. The algorithm can handle any arbitrary word length, with the required accuracy, at reasonable speed View full abstract»

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  • Compiler/hardware co-design for instruction boosting in ILP processors

    Publication Year: 1999 , Page(s): 269 - 274
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    One of the most important issues in instruction-level parallelism (ILP) processors involves the boosting of instructions across conditional branches for speculative execution. A compiler scheduling technique named LESS with a renaming function is proposed for the elimination of hazards that incorrectly overwrite a value when the branch is incorrectly predicted during speculative execution. The hardware implementation for this method is relatively simple and rather efficient. Simulation results show that the speedups achieved by LESS art better than other existing methods. For example, under the superscalar execution model, with an issue rate of 8, the average performance improvement by LESS can be expected to be 13% better than that of the CRF scheme, a solution reported recently with a scheduling skeleton similar to LESS View full abstract»

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  • Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs

    Publication Year: 1999 , Page(s): 309 - 315
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (596 KB)  

    The multiplier-free design of transforms implemented in LUT-based FPGAs is presented. To fit bit-level grain size in the FPGA device at algorithm level the authors use modified distributed arithmetic (DA) and a named adder-based DA to formulate bit-level transform expressions, then they further minimise hardware cost by the proposed vertical subexpression sharing. For implementation, the required input buffer design is also considered by employing FPGA device characteristics and cyclic formulation. The proposed design can offer savings in excess of two-thirds of hardware cost compared with ROM-based DA View full abstract»

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  • Automatic router for the pin grid array package

    Publication Year: 1999 , Page(s): 275 - 281
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    A pin grid array (PGA) package router is described. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment, topological routing and geometrical routing. Examples tested on a Windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router has a user-friendly graphic interface and can be applied practically to industrial strength VLSI packaging View full abstract»

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  • PASE-scan design: a new full-scan structure to reduce test application time

    Publication Year: 1999 , Page(s): 283 - 293
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (800 KB)  

    Serial scan approaches lead to a considerable reduction in the test generation cost for sequential circuits. However, they do present some drawbacks, such as area overhead I/O pin overhead and high test application time. A new full-scan approach is described named “PASE-scan design”, capable of substantially reducing the test application time. The paper focuses particularly on the case of single PASE-scan structures. An heuristic procedure is proposed to establish the configuration of the single PASE-scan structure and the placing of its memory elements. The experiments carried out with a set of ISCAS89 circuits show reductions in test length, with respect to the full single serial scan-path case, of up to 91% and 87%, depending on the compaction (low or normal) of the applied test set, and average reductions of 62% and 55%, respectively View full abstract»

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